[llvm] 8910349 - [RISCV][NFC] Set default value for BaseInstr in RISCVVPseudo
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 14 20:00:12 PDT 2022
Author: wangpc
Date: 2022-06-15T10:59:45+08:00
New Revision: 8910349e433a07488371f6f75e705033decc0e27
URL: https://github.com/llvm/llvm-project/commit/8910349e433a07488371f6f75e705033decc0e27
DIFF: https://github.com/llvm/llvm-project/commit/8910349e433a07488371f6f75e705033decc0e27.diff
LOG: [RISCV][NFC] Set default value for BaseInstr in RISCVVPseudo
Since almost all pseudos have the same form of BaseInstr, we
can just set it as default value to reduce some lines.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D127632
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 0ee84f29d159..72f2f595e79d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -46,6 +46,30 @@ defvar TAIL_AGNOSTIC = 1;
// Utilities.
//===----------------------------------------------------------------------===//
+class PseudoToVInst<string PseudoInst> {
+ string VInst = !subst("_M8", "",
+ !subst("_M4", "",
+ !subst("_M2", "",
+ !subst("_M1", "",
+ !subst("_MF2", "",
+ !subst("_MF4", "",
+ !subst("_MF8", "",
+ !subst("_B1", "",
+ !subst("_B2", "",
+ !subst("_B4", "",
+ !subst("_B8", "",
+ !subst("_B16", "",
+ !subst("_B32", "",
+ !subst("_B64", "",
+ !subst("_MASK", "",
+ !subst("_TIED", "",
+ !subst("_TU", "",
+ !subst("F16", "F",
+ !subst("F32", "F",
+ !subst("F64", "F",
+ !subst("Pseudo", "", PseudoInst)))))))))))))))))))));
+}
+
// This class describes information associated to the LMUL.
class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx> {
@@ -402,7 +426,7 @@ class CONST8b<bits<8> val> {
def InvalidIndex : CONST8b<0x80>;
class RISCVVPseudo {
Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key.
- Instruction BaseInstr;
+ Instruction BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
// The actual table.
@@ -580,30 +604,6 @@ def RISCVVSXSEGTable : GenericTable {
// Helpers to define the
diff erent pseudo instructions.
//===----------------------------------------------------------------------===//
-class PseudoToVInst<string PseudoInst> {
- string VInst = !subst("_M8", "",
- !subst("_M4", "",
- !subst("_M2", "",
- !subst("_M1", "",
- !subst("_MF2", "",
- !subst("_MF4", "",
- !subst("_MF8", "",
- !subst("_B1", "",
- !subst("_B2", "",
- !subst("_B4", "",
- !subst("_B8", "",
- !subst("_B16", "",
- !subst("_B32", "",
- !subst("_B64", "",
- !subst("_MASK", "",
- !subst("_TIED", "",
- !subst("_TU", "",
- !subst("F16", "F",
- !subst("F32", "F",
- !subst("F64", "F",
- !subst("Pseudo", "", PseudoInst)))))))))))))))))))));
-}
-
// The destination vector register group for a masked vector instruction cannot
// overlap the source mask register (v0), unless the destination vector register
// is being written with a mask value (e.g., comparisons) or the scalar result
@@ -654,7 +654,6 @@ class VPseudoUSLoadNoMask<VReg RetClass, int EEW, bit DummyMask = 1> :
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = DummyMask;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSLoadNoMaskTU<VReg RetClass, int EEW> :
@@ -670,7 +669,6 @@ class VPseudoUSLoadNoMaskTU<VReg RetClass, int EEW> :
let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSLoadMask<VReg RetClass, int EEW> :
@@ -689,7 +687,6 @@ class VPseudoUSLoadMask<VReg RetClass, int EEW> :
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSLoadFFNoMask<VReg RetClass, int EEW, bit DummyMask = 1> :
@@ -703,7 +700,6 @@ class VPseudoUSLoadFFNoMask<VReg RetClass, int EEW, bit DummyMask = 1> :
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = DummyMask;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSLoadFFNoMaskTU<VReg RetClass, int EEW> :
@@ -719,7 +715,6 @@ class VPseudoUSLoadFFNoMaskTU<VReg RetClass, int EEW> :
let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSLoadFFMask<VReg RetClass, int EEW> :
@@ -738,7 +733,6 @@ class VPseudoUSLoadFFMask<VReg RetClass, int EEW> :
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoSLoadNoMask<VReg RetClass, int EEW>:
@@ -752,7 +746,6 @@ class VPseudoSLoadNoMask<VReg RetClass, int EEW>:
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoSLoadNoMaskTU<VReg RetClass, int EEW>:
@@ -768,7 +761,6 @@ class VPseudoSLoadNoMaskTU<VReg RetClass, int EEW>:
let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoSLoadMask<VReg RetClass, int EEW>:
@@ -787,7 +779,6 @@ class VPseudoSLoadMask<VReg RetClass, int EEW>:
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoILoadNoMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -804,7 +795,6 @@ class VPseudoILoadNoMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
let HasSEWOp = 1;
let HasDummyMask = 1;
let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd", "");
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoILoadNoMaskTU<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -822,7 +812,6 @@ class VPseudoILoadNoMaskTU<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $dest", "$rd = $dest");
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoILoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -842,7 +831,6 @@ class VPseudoILoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSStoreNoMask<VReg StClass, int EEW, bit DummyMask = 1>:
@@ -856,7 +844,6 @@ class VPseudoUSStoreNoMask<VReg StClass, int EEW, bit DummyMask = 1>:
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = DummyMask;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSStoreMask<VReg StClass, int EEW>:
@@ -869,7 +856,6 @@ class VPseudoUSStoreMask<VReg StClass, int EEW>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoSStoreNoMask<VReg StClass, int EEW>:
@@ -883,7 +869,6 @@ class VPseudoSStoreNoMask<VReg StClass, int EEW>:
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoSStoreMask<VReg StClass, int EEW>:
@@ -896,7 +881,6 @@ class VPseudoSStoreMask<VReg StClass, int EEW>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
// Unary instruction that is never masked so HasDummyMask=0.
@@ -910,7 +894,6 @@ class VPseudoUnaryNoDummyMask<VReg RetClass,
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUnaryNoDummyMaskTU<VReg RetClass,
@@ -925,7 +908,6 @@ class VPseudoUnaryNoDummyMaskTU<VReg RetClass,
let HasSEWOp = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoNullaryNoMask<VReg RegClass>:
@@ -938,7 +920,6 @@ class VPseudoNullaryNoMask<VReg RegClass>:
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoNullaryNoMaskTU<VReg RegClass>:
@@ -953,7 +934,6 @@ class VPseudoNullaryNoMaskTU<VReg RegClass>:
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoNullaryMask<VReg RegClass>:
@@ -969,7 +949,6 @@ class VPseudoNullaryMask<VReg RegClass>:
let HasMergeOp = 1;
let UsesMaskPolicy = 1;
let HasVecPolicyOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
// Nullary for pseudo instructions. They are expanded in
@@ -999,7 +978,6 @@ class VPseudoUnaryNoMask<DAGOperand RetClass, VReg OpClass, string Constraint =
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
// RetClass could be GPR or VReg.
@@ -1015,7 +993,6 @@ class VPseudoUnaryNoMaskTU<DAGOperand RetClass, VReg OpClass, string Constraint
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
@@ -1031,7 +1008,6 @@ class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
let HasSEWOp = 1;
let HasMergeOp = 1;
let UsesMaskPolicy = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUnaryMaskTA<VReg RetClass, VReg OpClass, string Constraint = ""> :
@@ -1048,7 +1024,6 @@ class VPseudoUnaryMaskTA<VReg RetClass, VReg OpClass, string Constraint = ""> :
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
// mask unary operation without maskedoff
@@ -1061,7 +1036,6 @@ class VPseudoMaskUnarySOutMask:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
// Mask can be V0~V31
@@ -1080,7 +1054,6 @@ class VPseudoUnaryAnyMask<VReg RetClass,
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoBinaryNoMask<VReg RetClass,
@@ -1098,7 +1071,6 @@ class VPseudoBinaryNoMask<VReg RetClass,
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = DummyMask;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoBinaryNoMaskTU<VReg RetClass,
@@ -1116,7 +1088,6 @@ class VPseudoBinaryNoMaskTU<VReg RetClass,
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
// Special version of VPseudoBinaryNoMask where we pretend the first source is
@@ -1137,7 +1108,6 @@ class VPseudoTiedBinaryNoMask<VReg RetClass,
let HasDummyMask = 1;
let ForceTailAgnostic = 1;
let isConvertibleToThreeAddress = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoTiedBinaryNoMaskTU<VReg RetClass,
@@ -1156,7 +1126,6 @@ class VPseudoTiedBinaryNoMaskTU<VReg RetClass,
let HasSEWOp = 1;
let HasMergeOp = 0; // Merge is also rs2.
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -1171,7 +1140,6 @@ class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -1185,7 +1153,6 @@ class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoBinaryMask<VReg RetClass,
@@ -1204,7 +1171,6 @@ class VPseudoBinaryMask<VReg RetClass,
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoBinaryMaskPolicy<VReg RetClass,
@@ -1225,7 +1191,6 @@ class VPseudoBinaryMaskPolicy<VReg RetClass,
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
// Like VPseudoBinaryMask, but output can be V0.
@@ -1246,7 +1211,6 @@ class VPseudoBinaryMOutMask<VReg RetClass,
let HasSEWOp = 1;
let HasMergeOp = 1;
let UsesMaskPolicy = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
// Special version of VPseudoBinaryMask where we pretend the first source is
@@ -1269,7 +1233,6 @@ class VPseudoTiedBinaryMask<VReg RetClass,
let HasMergeOp = 0; // Merge is also rs2.
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoBinaryCarryIn<VReg RetClass,
@@ -1291,7 +1254,6 @@ class VPseudoBinaryCarryIn<VReg RetClass,
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 0;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
let VLMul = MInfo.value;
}
@@ -1315,7 +1277,6 @@ class VPseudoTiedBinaryCarryIn<VReg RetClass,
let HasSEWOp = 1;
let HasMergeOp = 1;
let HasVecPolicyOp = 0;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
let VLMul = MInfo.value;
}
@@ -1336,7 +1297,6 @@ class VPseudoTernaryNoMask<VReg RetClass,
let HasSEWOp = 1;
let HasMergeOp = 1;
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
@@ -1357,7 +1317,6 @@ class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
let HasSEWOp = 1;
let HasMergeOp = 1;
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSSegLoadNoMask<VReg RetClass, int EEW, bits<4> NF>:
@@ -1371,7 +1330,6 @@ class VPseudoUSSegLoadNoMask<VReg RetClass, int EEW, bits<4> NF>:
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSSegLoadNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
@@ -1387,7 +1345,6 @@ class VPseudoUSSegLoadNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSSegLoadMask<VReg RetClass, int EEW, bits<4> NF>:
@@ -1405,7 +1362,6 @@ class VPseudoUSSegLoadMask<VReg RetClass, int EEW, bits<4> NF>:
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSSegLoadFFNoMask<VReg RetClass, int EEW, bits<4> NF>:
@@ -1419,7 +1375,6 @@ class VPseudoUSSegLoadFFNoMask<VReg RetClass, int EEW, bits<4> NF>:
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSSegLoadFFNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
@@ -1435,7 +1390,6 @@ class VPseudoUSSegLoadFFNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSSegLoadFFMask<VReg RetClass, int EEW, bits<4> NF>:
@@ -1453,7 +1407,6 @@ class VPseudoUSSegLoadFFMask<VReg RetClass, int EEW, bits<4> NF>:
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoSSegLoadNoMask<VReg RetClass, int EEW, bits<4> NF>:
@@ -1468,7 +1421,6 @@ class VPseudoSSegLoadNoMask<VReg RetClass, int EEW, bits<4> NF>:
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoSSegLoadNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
@@ -1485,7 +1437,6 @@ class VPseudoSSegLoadNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $merge";
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoSSegLoadMask<VReg RetClass, int EEW, bits<4> NF>:
@@ -1504,7 +1455,6 @@ class VPseudoSSegLoadMask<VReg RetClass, int EEW, bits<4> NF>:
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoISegLoadNoMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -1522,7 +1472,6 @@ class VPseudoISegLoadNoMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoISegLoadNoMaskTU<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -1541,7 +1490,6 @@ class VPseudoISegLoadNoMaskTU<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMU
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoISegLoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -1563,7 +1511,6 @@ class VPseudoISegLoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSSegStoreNoMask<VReg ValClass, int EEW, bits<4> NF>:
@@ -1577,7 +1524,6 @@ class VPseudoUSSegStoreNoMask<VReg ValClass, int EEW, bits<4> NF>:
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSSegStoreMask<VReg ValClass, int EEW, bits<4> NF>:
@@ -1591,7 +1537,6 @@ class VPseudoUSSegStoreMask<VReg ValClass, int EEW, bits<4> NF>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoSSegStoreNoMask<VReg ValClass, int EEW, bits<4> NF>:
@@ -1605,7 +1550,6 @@ class VPseudoSSegStoreNoMask<VReg ValClass, int EEW, bits<4> NF>:
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoSSegStoreMask<VReg ValClass, int EEW, bits<4> NF>:
@@ -1619,7 +1563,6 @@ class VPseudoSSegStoreMask<VReg ValClass, int EEW, bits<4> NF>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoISegStoreNoMask<VReg ValClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -1635,7 +1578,6 @@ class VPseudoISegStoreNoMask<VReg ValClass, VReg IdxClass, int EEW, bits<3> LMUL
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoISegStoreMask<VReg ValClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -1650,7 +1592,6 @@ class VPseudoISegStoreMask<VReg ValClass, VReg IdxClass, int EEW, bits<3> LMUL,
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
multiclass VPseudoUSLoad {
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