[PATCH] D127721: [RISCV][NFC] Add load/store instructions in rv64*-invalid.s
Ben Shi via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 14 18:23:23 PDT 2022
benshi001 added inline comments.
================
Comment at: llvm/test/MC/RISCV/rv64zdinx-invalid.s:4
+# Not support float registers
+flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
+
----------------
sunshaoce wrote:
> benshi001 wrote:
> > I guess you probably want `fld` and `fsd` ?
> In zdinx, you should use `ld` rather than `fld` or `flw`.
Sure. So we need to test neither fld/fsd nor fsw/flw is valid.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D127721/new/
https://reviews.llvm.org/D127721
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