[PATCH] D126807: [PowerPC] Fix LQ-STQ instructions to use correct offset and base

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai requested changes to this revision.
nemanjai added a comment.
This revision now requires changes to proceed.

If this IR is compiled with `-mattr=+quadword-atomics`, we emit `#STQX_PSEUDO` which is definitely not what we want:

  %struct.StructA = type { [16 x i8] }
  
  @s1 = dso_local global i128 324929342, align 16
  
  ; Function Attrs: mustprogress noinline nounwind optnone uwtable
  define dso_local void @_Z4testv() #0 {
  entry:
    %s2 = alloca %struct.StructA, align 16
    %s3 = alloca %struct.StructA, align 16
    %arr = alloca [997003 x i8], align 1
    %tmp = alloca %struct.StructA, align 16
    call void @llvm.memcpy.p0.p0.i64(ptr align 16 %tmp, ptr align 16 @s1, i64 16, i1 false)
    %0 = load i128, ptr %tmp, align 16
    store atomic i128 %0, ptr %s2 seq_cst, align 16
    ret void
  }
  
  ; Function Attrs: argmemonly nofree nounwind willreturn
  declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1
  
  attributes #0 = { noinline optnone }



================
Comment at: llvm/test/CodeGen/PowerPC/LQ-STQ-32bit-offset.ll:34
+
+attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr10" "target-features"="+altivec,+bpermd,+crbits,+crypto,+direct-move,+extdiv,+isa-v206-instructions,+isa-v207-instructions,+isa-v30-instructions,+isa-v31-instructions,+mma,+paired-vector-memops,+pcrelative-memops,+power10-vector,+power8-vector,+power9-vector,+prefix-instrs,+quadword-atomics,+vsx,-htm,-privileged,-rop-protect,-spe" }
----------------
Please get rid of all of this and just compile with `-mcpu=pwr10`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126807/new/

https://reviews.llvm.org/D126807