[PATCH] D127697: [AMDGPU] gfx11 support add_f16

[Joe Nash via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG989bd57f9879: [AMDGPU] gfx11 support add_f16 (authored by Joe_Nash).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127697/new/

https://reviews.llvm.org/D127697

Files:
  llvm/lib/Target/AMDGPU/VOP2Instructions.td
  llvm/test/MC/AMDGPU/gfx11_asm_dpp16.s
  llvm/test/MC/AMDGPU/gfx11_asm_dpp8.s
  llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_all.txt


Index: llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_all.txt
===================================================================
--- llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_all.txt
+++ llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_all.txt
@@ -46334,6 +46334,12 @@
 # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0x00]
 0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0x00
 
+# GFX11: v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0x00]
+0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0x00
+
+# GFX11: v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x04,0x00]
+0xfa,0x04,0x0a,0x64,0x01,0x1b,0x04,0x00
+
 # GFX11: v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0x00]
 0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0x00
 
@@ -46951,6 +46957,12 @@
 # GFX11: v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x04,0x00]
 0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x04,0x00
 
+# GFX11: v_add_f16_dpp v5, v1, v2 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0x04,0x0a,0x64,0x01,0x88,0xc6,0xfa]
+0xe9,0x04,0x0a,0x64,0x01,0x88,0xc6,0xfa
+
+# GFX11: v_add_f16_dpp v5, v1, v2 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x04,0x0a,0x64,0x01,0x88,0xc6,0xfa]
+0xea,0x04,0x0a,0x64,0x01,0x88,0xc6,0xfa
+
 # GFX11: v_add_f32_dpp v5, v1, v2 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0x04,0x0a,0x06,0x01,0x88,0xc6,0xfa]
 0xe9,0x04,0x0a,0x06,0x01,0x88,0xc6,0xfa
 
Index: llvm/test/MC/AMDGPU/gfx11_asm_dpp8.s
===================================================================
--- llvm/test/MC/AMDGPU/gfx11_asm_dpp8.s
+++ llvm/test/MC/AMDGPU/gfx11_asm_dpp8.s
@@ -228,6 +228,9 @@
 v_xnor_b32 v5, v1, v2 dpp8:[0,1,2,3,4,5,6,7]
 // GFX11: encoding: [0xe9,0x04,0x0a,0x3c,0x01,0x88,0xc6,0xfa]
 
+v_add_f16 v5, v1, v2 dpp8:[0,1,2,3,4,5,6,7]
+// GFX11: encoding: [0xe9,0x04,0x0a,0x64,0x01,0x88,0xc6,0xfa]
+
 v_sub_f16 v5, v1, v2 dpp8:[0,1,2,3,4,5,6,7]
 // GFX11: encoding: [0xe9,0x04,0x0a,0x66,0x01,0x88,0xc6,0xfa]
 
@@ -477,6 +480,9 @@
 v_xnor_b32 v5, v1, v2 dpp8:[0,1,2,3,4,5,6,7] fi:1
 // GFX11: encoding: [0xea,0x04,0x0a,0x3c,0x01,0x88,0xc6,0xfa]
 
+v_add_f16 v5, v1, v2 dpp8:[0,1,2,3,4,5,6,7] fi:1
+// GFX11: encoding: [0xea,0x04,0x0a,0x64,0x01,0x88,0xc6,0xfa]
+
 v_sub_f16 v5, v1, v2 dpp8:[0,1,2,3,4,5,6,7] fi:1
 // GFX11: encoding: [0xea,0x04,0x0a,0x66,0x01,0x88,0xc6,0xfa]
 
Index: llvm/test/MC/AMDGPU/gfx11_asm_dpp16.s
===================================================================
--- llvm/test/MC/AMDGPU/gfx11_asm_dpp16.s
+++ llvm/test/MC/AMDGPU/gfx11_asm_dpp16.s
@@ -312,6 +312,9 @@
 v_fmac_f32 v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 // GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0x00]
 
+v_add_f16 v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0x00]
+
 v_sub_f16 v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 // GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0x00]
 
@@ -570,6 +573,9 @@
 v_fmac_f32 v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 // GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x04,0x00]
 
+v_add_f16 v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
+// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x04,0x00]
+
 v_sub_f16 v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 // GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x04,0x00]
 
Index: llvm/lib/Target/AMDGPU/VOP2Instructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -1548,7 +1548,7 @@
 defm V_FMAC_F32        : VOP2_Real_gfx10_gfx11<0x02b>;
 defm V_FMAMK_F32       : VOP2Only_Real_MADK_gfx10_gfx11<0x02c>;
 defm V_FMAAK_F32       : VOP2Only_Real_MADK_gfx10_gfx11<0x02d>;
-defm V_ADD_F16         : VOP2_Real_gfx10<0x032>;
+defm V_ADD_F16         : VOP2_Real_gfx10_gfx11<0x032>;
 defm V_SUB_F16         : VOP2_Real_gfx10_gfx11<0x033>;
 defm V_SUBREV_F16      : VOP2_Real_gfx10_gfx11<0x034>;
 defm V_MUL_F16         : VOP2_Real_gfx10_gfx11<0x035>;


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