[PATCH] D127414: [AArch64][SME] Add SME read/write intrinsics that map to the mova instruction

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:611-625
+multiclass sme_vector_to_tile_q_patterns<Instruction inst, ValueType zpr_vt,
+                                         ValueType ppr_vt, Operand imm_ty,
+                                         Operand offset_ty,
+                                         SDPatternOperator op,
+                                         ComplexPattern tileslice> {
+  def : Pat<(op imm_ty:$tile, MatrixIndexGPR32Op12_15:$idx,
+                (ppr_vt PPR3bAny:$pg), (zpr_vt ZPRAny:$zn)),
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aemerson wrote:
> Do my eyes deceive me or is this the same as `sme_vector_to_tile_patterns`?
Good point - they are the same! :facepalm


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:778-789
+  defm : sme_vector_to_tile_q_patterns<!cast<Instruction>(NAME # _PSEUDO_Q),
+                                     nxv2i64, nxv2i1, sme_elm_idx0_15,
+                                     sme_elm_idx0_0,
+                                     !if(is_col, int_aarch64_sme_writeq_vert,
+                                                 int_aarch64_sme_writeq_horiz),
+                                     tileslice128>;
+  defm : sme_vector_to_tile_q_patterns<!cast<Instruction>(NAME # _PSEUDO_Q),
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c-rhodes wrote:
> these two are the same?
No, they're different. One is nxv2i64 and the other is nxv2f64.


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:993-1002
+  defm : sme_tile_to_vector_q_patterns<!cast<Instruction>(NAME # _Q),
+                                       nxv2f64, nxv2i1, sme_elm_idx0_0,
+                                       imm_to_tile128, tileslice128,
+                                       !if(is_col, int_aarch64_sme_readq_vert,
+                                                   int_aarch64_sme_readq_horiz)>;
+  defm : sme_tile_to_vector_q_patterns<!cast<Instruction>(NAME # _Q),
+                                       nxv2f64, nxv2i1, sme_elm_idx0_0,
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c-rhodes wrote:
> also the same
Yep, these two are definitely the same. :)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127414/new/

https://reviews.llvm.org/D127414