[PATCH] D127414: [AArch64][SME] Add SME read/write intrinsics that map to the mova instruction

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added inline comments.


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:704-705
+                                     nxv16i8, nxv16i1, sme_elm_idx0_0, imm0_15,
+                                     !if(is_col, int_aarch64_sme_write_vert,
+                                                 int_aarch64_sme_write_horiz),
+                                     tileslice8>;
----------------
this is repeated a bunch how about doing:

```  defvar op = !if(is_col, int_aarch64_sme_write_vert,
                          int_aarch64_sme_write_horiz);```

above and replacing uses with op to clean it up a bit?


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:743-747
+                                     nxv16i8, nxv16i1, sme_elm_idx0_15,
+                                     sme_elm_idx0_0,
+                                     !if(is_col, int_aarch64_sme_writeq_vert,
+                                                 int_aarch64_sme_writeq_horiz),
+                                     tileslice128>;
----------------
nit: alignment, but it looks like this q_patterns class can be removed as Amara noticed.


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:778-789
+  defm : sme_vector_to_tile_q_patterns<!cast<Instruction>(NAME # _PSEUDO_Q),
+                                     nxv2i64, nxv2i1, sme_elm_idx0_15,
+                                     sme_elm_idx0_0,
+                                     !if(is_col, int_aarch64_sme_writeq_vert,
+                                                 int_aarch64_sme_writeq_horiz),
+                                     tileslice128>;
+  defm : sme_vector_to_tile_q_patterns<!cast<Instruction>(NAME # _PSEUDO_Q),
----------------
these two are the same?


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:993-1002
+  defm : sme_tile_to_vector_q_patterns<!cast<Instruction>(NAME # _Q),
+                                       nxv2f64, nxv2i1, sme_elm_idx0_0,
+                                       imm_to_tile128, tileslice128,
+                                       !if(is_col, int_aarch64_sme_readq_vert,
+                                                   int_aarch64_sme_readq_horiz)>;
+  defm : sme_tile_to_vector_q_patterns<!cast<Instruction>(NAME # _Q),
+                                       nxv2f64, nxv2i1, sme_elm_idx0_0,
----------------
also the same


================
Comment at: llvm/test/CodeGen/AArch64/SME/sme-intrinsics-mova-extract.ll:298
+
+define <vscale x 16 x i8> @extract_row_q_16i18(<vscale x 16 x i8> %zd, <vscale x 16 x i1> %pg) {
+; CHECK-LABEL: extract_row_q_16i18:
----------------
16i8

the insert tests also prefix this with 'v'


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127414/new/

https://reviews.llvm.org/D127414