[llvm] 62b3d8d - [TableGen] const char *const x => const char x[]

Robinson, Paul via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 13 13:33:24 PDT 2022


Part of this change look okay (NFC) but other parts are not.

> -----Original Message-----
> From: llvm-commits <llvm-commits-bounces at lists.llvm.org> On Behalf Of
> Fangrui Song via llvm-commits
> Sent: Friday, June 10, 2022 10:14 PM
> To: llvm-commits at lists.llvm.org
> Subject: [llvm] 62b3d8d - [TableGen] const char *const x => const char x[]
> 
> 
> Author: Fangrui Song
> Date: 2022-06-10T19:13:59-07:00
> New Revision: 62b3d8d10a04584c93875d9579f3d7fa273c3a2a
> 
> URL: https://urldefense.com/v3/__https://github.com/llvm/llvm-
> project/commit/62b3d8d10a04584c93875d9579f3d7fa273c3a2a__;!!JmoZiZGBv3RvKR
> Sx!_9wnYKJe8jH2vyvClJDSwaIikU7OfjU7aG5wrowNf3gehctaVOb3DumNKLEhrqAFwLcHuHU
> -yG7bdXKNYzaJ26Veb750$
> DIFF: https://urldefense.com/v3/__https://github.com/llvm/llvm-
> project/commit/62b3d8d10a04584c93875d9579f3d7fa273c3a2a.diff__;!!JmoZiZGBv
> 3RvKRSx!_9wnYKJe8jH2vyvClJDSwaIikU7OfjU7aG5wrowNf3gehctaVOb3DumNKLEhrqAFwL
> cHuHU-yG7bdXKNYzaJ2613q1d2$
> 
> LOG: [TableGen] const char *const x => const char x[]
> 
> Added:
> 
> 
> Modified:
>     llvm/test/TableGen/MixedCasedMnemonic.td
>     llvm/test/TableGen/bare-minimum-psets.td
>     llvm/test/TableGen/inhibit-pset.td
>     llvm/utils/TableGen/AsmMatcherEmitter.cpp
>     llvm/utils/TableGen/CodeGenTarget.cpp
>     llvm/utils/TableGen/RegisterInfoEmitter.cpp
> 
> Removed:
> 
> 
> 
> ##########################################################################
> ######
> diff  --git a/llvm/test/TableGen/MixedCasedMnemonic.td
> b/llvm/test/TableGen/MixedCasedMnemonic.td
> index 3dd6a210aa622..3dc44ab6052c3 100644
> --- a/llvm/test/TableGen/MixedCasedMnemonic.td
> +++ b/llvm/test/TableGen/MixedCasedMnemonic.td
> @@ -40,7 +40,7 @@ def :MnemonicAlias<"Insta", "aInst">;
>  def :MnemonicAlias<"InstB", "BInst">;
> 
>  // Check that the matcher lower()s the mnemonics it matches.
> -// MATCHER: static const char *const MnemonicTable =
> +// MATCHER: static const char MnemonicTable[] =

Semantically equivalent, this is fine.

>  // MATCHER-NEXT: "\005ainst\005binst";
> 
>  // Check that aInst appears before BInst in the match table.
> 
> diff  --git a/llvm/test/TableGen/bare-minimum-psets.td
> b/llvm/test/TableGen/bare-minimum-psets.td
> index e5c842cd1e301..25e0bd2a83d1d 100644
> --- a/llvm/test/TableGen/bare-minimum-psets.td
> +++ b/llvm/test/TableGen/bare-minimum-psets.td
> @@ -48,7 +48,7 @@ def MyTarget : Target;
>  // NAMESPACE-NEXT: } // end namespace TestNamespace
> 
>  // CHECK-LABEL: getRegPressureSetName(unsigned Idx) const {
> -// CHECK-NEXT:    static const char *const PressureNameTable[] = {
> +// CHECK-NEXT:    static const char *PressureNameTable[] = {

This is a semantic change. Instead of an array of const pointers,
which could be allocated to a readonly section, it is now an array 
of (modifiable) pointers that must be in a writable section.  
It would be safer to leave this as const pointers.

>  // CHECK-NEXT:      "D_32",
>  // CHECK-NEXT:    };
>  // CHECK-NEXT:    return PressureNameTable[Idx];
> 
> diff  --git a/llvm/test/TableGen/inhibit-pset.td
> b/llvm/test/TableGen/inhibit-pset.td
> index d9f56137db7a7..1f4f8a176c62c 100644
> --- a/llvm/test/TableGen/inhibit-pset.td
> +++ b/llvm/test/TableGen/inhibit-pset.td
> @@ -8,7 +8,7 @@ include "reg-with-subregs-common.td"
>  def X0 : Register <"x0">;
> 
>  // CHECK-LABEL: getRegPressureSetName(unsigned Idx) const {
> -// CHECK-NEXT:    static const char *const PressureNameTable[] = {
> +// CHECK-NEXT:    static const char *PressureNameTable[] = {

Same semantic change here.

>  // CHECK-NEXT:      "GPR32",
>  // CHECK-NEXT:    };
>  // CHECK-NEXT:    return PressureNameTable[Idx];
> 
> diff  --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
> b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
> index 2c2239f2b6b44..1acc2a86d176f 100644
> --- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
> +++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
> @@ -3395,7 +3395,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
>                          StringTable.GetOrAddStringOffset(LenMnemonic,
> false));
>    }
> 
> -  OS << "static const char *const MnemonicTable =\n";
> +  OS << "static const char MnemonicTable[] =\n";
>    StringTable.EmitString(OS);
>    OS << ";\n\n";
> 
> 
> diff  --git a/llvm/utils/TableGen/CodeGenTarget.cpp
> b/llvm/utils/TableGen/CodeGenTarget.cpp
> index 65ccb742b1f32..6c1b021a2b443 100644
> --- a/llvm/utils/TableGen/CodeGenTarget.cpp
> +++ b/llvm/utils/TableGen/CodeGenTarget.cpp
> @@ -474,7 +474,7 @@ GetInstByName(const char *Name,
>    return I->second.get();
>  }
> 
> -static const char *const FixedInstrs[] = {
> +static const char *FixedInstrs[] = {

Same semantic change, this time in the implementation not the
generated source.

>  #define HANDLE_TARGET_OPCODE(OPC) #OPC,
>  #include "llvm/Support/TargetOpcodes.def"
>      nullptr};
> 
> diff  --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
> b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
> index 0ba6dee9f7d69..3a0fa564074e8 100644
> --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
> +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
> @@ -268,7 +268,7 @@ EmitRegUnitPressure(raw_ostream &OS, const
> CodeGenRegBank &RegBank,
>    OS << "// Get the name of this register unit pressure set.\n"
>       << "const char *" << ClassName << "::\n"
>       << "getRegPressureSetName(unsigned Idx) const {\n"
> -     << "  static const char *const PressureNameTable[] = {\n";
> +     << "  static const char *PressureNameTable[] = {\n";

And here

>    unsigned MaxRegUnitWeight = 0;
>    for (unsigned i = 0; i < NumSets; ++i ) {
>      const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
> @@ -1264,7 +1264,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS,
> CodeGenTarget &Target,
>    OS << "};\n";
> 
>    // Emit SubRegIndex names, skipping 0.
> -  OS << "\nstatic const char *const SubRegIndexNameTable[] = { \"";
> +  OS << "\nstatic const char *SubRegIndexNameTable[] = { \"";

And here

> 
>    for (const auto &Idx : SubRegIndices) {
>      OS << Idx.getName();
> @@ -1681,7 +1681,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS,
> CodeGenTarget &Target,
>    OS << "ArrayRef<const char *> " << ClassName
>       << "::getRegMaskNames() const {\n";
>    if (!CSRSets.empty()) {
> -  OS << "  static const char *const Names[] = {\n";
> +    OS << "  static const char *Names[] = {\n";

And here

>      for (Record *CSRSet : CSRSets)
>        OS << "    " << '"' << CSRSet->getName() << '"' << ",\n";
>      OS << "  };\n";

--paulr



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