[PATCH] D127527: [AMDGPU] Define SGPR_NULL64 register. NFCI.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D127527#3579423 <https://reviews.llvm.org/D127527#3579423>, @foad wrote:

> I guess this is OK. I'm a bit surprised that null is defined like a real physical register, but I guess it has always worked this way. And MIPS seems to do the same for their r0 register which works the same way.

It is in fact a real HW register, although quite special. Anyway we need to fit it into an operand, it needs to be a part of actual RC, and size shall match.


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