[PATCH] D127527: [AMDGPU] Define SGPR_NULL64 register. NFCI.

Jay Foad via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 13 12:58:21 PDT 2022


foad accepted this revision.
foad added a comment.
This revision is now accepted and ready to land.

I guess this is OK. I'm a bit surprised that null is defined like a real physical register, but I guess it has always worked this way. And MIPS seems to do the same for their r0 register which works the same way.


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