[PATCH] D127115: [RFC][DAGCombine] Make sure combined nodes are added back to the worklist in topological order.

Sun Jun 12 14:24:10 PDT 2022

deadalnix updated this revision to Diff 436250.
deadalnix added a comment.

Reabse on top of D127595 <https://reviews.llvm.org/D127595>

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127115/new/

https://reviews.llvm.org/D127115

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
  llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
  llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
  llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
  llvm/test/CodeGen/AMDGPU/ds-alignment.ll
  llvm/test/CodeGen/AMDGPU/ds_write2.ll
  llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
  llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
  llvm/test/CodeGen/AMDGPU/store-local.128.ll
  llvm/test/CodeGen/AMDGPU/store-local.96.ll
  llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
  llvm/test/CodeGen/ARM/addsubcarry-promotion.ll
  llvm/test/CodeGen/ARM/dsp-mlal.ll
  llvm/test/CodeGen/ARM/neon-copy.ll
  llvm/test/CodeGen/ARM/vdup.ll
  llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
  llvm/test/CodeGen/PowerPC/combine-fneg.ll
  llvm/test/CodeGen/PowerPC/prefer-dqform.ll
  llvm/test/CodeGen/PowerPC/select_const.ll
  llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
  llvm/test/CodeGen/PowerPC/testComparesigeui.ll
  llvm/test/CodeGen/PowerPC/testComparesigeus.ll
  llvm/test/CodeGen/PowerPC/testComparesileuc.ll
  llvm/test/CodeGen/PowerPC/testComparesileui.ll
  llvm/test/CodeGen/PowerPC/testComparesileus.ll
  llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
  llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
  llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
  llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
  llvm/test/CodeGen/PowerPC/testComparesllleui.ll
  llvm/test/CodeGen/PowerPC/testComparesllleus.ll
  llvm/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll
  llvm/test/CodeGen/RISCV/mul.ll
  llvm/test/CodeGen/SystemZ/pr36164.ll
  llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
  llvm/test/CodeGen/Thumb2/mve-vqdmulh-minmax.ll
  llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll
  llvm/test/CodeGen/WebAssembly/simd-build-vector.ll
  llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
  llvm/test/CodeGen/X86/2012-08-07-CmpISelBug.ll
  llvm/test/CodeGen/X86/addcarry.ll
  llvm/test/CodeGen/X86/avx512-build-vector.ll
  llvm/test/CodeGen/X86/avx512-hadd-hsub.ll
  llvm/test/CodeGen/X86/avx512-mask-op.ll
  llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
  llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
  llvm/test/CodeGen/X86/bitreverse.ll
  llvm/test/CodeGen/X86/combine-fcopysign.ll
  llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
  llvm/test/CodeGen/X86/dagcombine-select.ll
  llvm/test/CodeGen/X86/field-extract-use-trunc.ll
  llvm/test/CodeGen/X86/haddsub-undef.ll
  llvm/test/CodeGen/X86/horizontal-sum.ll
  llvm/test/CodeGen/X86/insertelement-var-index.ll
  llvm/test/CodeGen/X86/is_fpclass-fp80.ll
  llvm/test/CodeGen/X86/isel-blendi-gettargetconstant.ll
  llvm/test/CodeGen/X86/load-partial.ll
  llvm/test/CodeGen/X86/movmsk-cmp.ll
  llvm/test/CodeGen/X86/mulvi32.ll
  llvm/test/CodeGen/X86/nontemporal-3.ll
  llvm/test/CodeGen/X86/pmulh.ll
  llvm/test/CodeGen/X86/popcnt.ll
  llvm/test/CodeGen/X86/pr42727.ll
  llvm/test/CodeGen/X86/pr53419.ll
  llvm/test/CodeGen/X86/promote-vec3.ll
  llvm/test/CodeGen/X86/psubus.ll
  llvm/test/CodeGen/X86/shift-mask.ll
  llvm/test/CodeGen/X86/shuffle-extract-subvector.ll
  llvm/test/CodeGen/X86/sse41.ll
  llvm/test/CodeGen/X86/vec_saddo.ll
  llvm/test/CodeGen/X86/vec_smulo.ll
  llvm/test/CodeGen/X86/vec_ssubo.ll
  llvm/test/CodeGen/X86/vec_uaddo.ll
  llvm/test/CodeGen/X86/vec_umulo.ll
  llvm/test/CodeGen/X86/vec_usubo.ll
  llvm/test/CodeGen/X86/vector-bitreverse.ll
  llvm/test/CodeGen/X86/vector-fshl-256.ll
  llvm/test/CodeGen/X86/vector-fshl-512.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
  llvm/test/CodeGen/X86/vector-fshr-256.ll
  llvm/test/CodeGen/X86/vector-fshr-512.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
  llvm/test/CodeGen/X86/vector-reduce-and-cmp.ll
  llvm/test/CodeGen/X86/vector-reduce-and.ll
  llvm/test/CodeGen/X86/vector-reduce-or.ll
  llvm/test/CodeGen/X86/vector-reduce-xor.ll
  llvm/test/CodeGen/X86/vector-rotate-256.ll
  llvm/test/CodeGen/X86/vector-rotate-512.ll
  llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining.ll
  llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll
  llvm/test/CodeGen/X86/vector-zext.ll
  llvm/test/CodeGen/X86/vselect-constants.ll
  llvm/test/CodeGen/X86/xor.ll

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