[PATCH] D127563: [PowerPC] Fix llvm.ppc.cfence on float point types

[Kai Luo via Phabricator via llvm-commits]

lkail created this revision.
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Handle `llvm.ppc.cfence` on `f64` and `f32` values bitcasted from integer values.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127563

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/cfence-double.ll
  llvm/test/CodeGen/PowerPC/cfence-float.ll


Index: llvm/test/CodeGen/PowerPC/cfence-float.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/cfence-float.ll
+++ llvm/test/CodeGen/PowerPC/cfence-float.ll
@@ -1,11 +1,17 @@
-; REQUIRES: asserts
-; RUN: not --crash llc -opaque-pointers -mtriple=powerpc64le-unknown-unknown \
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -opaque-pointers -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   < %s 2>&1 | FileCheck %s
-; RUN: not --crash llc -opaque-pointers -mtriple=powerpc64-unknown-unknown \
+; RUN: llc -opaque-pointers -mtriple=powerpc64-unknown-unknown \
 ; RUN:   < %s 2>&1 | FileCheck %s
 
-; CHECK: Assertion `VT.isInteger() && Operand.getValueType().isInteger() && "Invalid ANY_EXTEND!"' failed
 define void @bar() {
+; CHECK-LABEL: bar:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    cmpd 7, 3, 3
+; CHECK-NEXT:    bne- 7, .+4
+; CHECK-NEXT:    isync
+; CHECK-NEXT:    blr
 entry:
   %0 = load atomic float, float* undef acquire, align 8
   ret void
Index: llvm/test/CodeGen/PowerPC/cfence-double.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/cfence-double.ll
+++ llvm/test/CodeGen/PowerPC/cfence-double.ll
@@ -1,11 +1,17 @@
-; REQUIRES: asserts
-; RUN: not --crash llc -opaque-pointers -mtriple=powerpc64le-unknown-unknown \
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -opaque-pointers -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   < %s 2>&1 | FileCheck %s
-; RUN: not --crash llc -opaque-pointers -mtriple=powerpc64-unknown-unknown \
+; RUN: llc -opaque-pointers -mtriple=powerpc64-unknown-unknown \
 ; RUN:   < %s 2>&1 | FileCheck %s
 
-; CHECK: Assertion `VT.isInteger() && Operand.getValueType().isInteger() && "Invalid ANY_EXTEND!"' failed
 define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ld 3, 0(3)
+; CHECK-NEXT:    cmpd 7, 3, 3
+; CHECK-NEXT:    bne- 7, .+4
+; CHECK-NEXT:    isync
+; CHECK-NEXT:    blr
 entry:
   %0 = load atomic double, double* undef acquire, align 8
   ret void
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10684,7 +10684,14 @@
       // FIXME: Testing one of two paired registers is sufficient to guarantee
       // ordering?
       Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, Val);
-    }
+    } else if (Ty == MVT::f32 || Ty == MVT::f64) {
+      assert(Val.getOpcode() == ISD::BITCAST &&
+             "Expect the float point value is bitcasted from another value.");
+      Val = Val.getOperand(0);
+      assert(Val.getValueType().isInteger() &&
+             "Expect the float point value is bitcasted from a integer value");
+    } else if (!Ty.isInteger())
+      llvm_unreachable("Unhandled type in llvm.ppc.cfence");
     return SDValue(
         DAG.getMachineNode(PPC::CFENCE8, DL, MVT::Other,
                            DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Val),


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