[PATCH] D127549: RISCV: handle 64-bit PCREL data relocations

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp:236
+    // Avoid relaxation for symbolic difference in debug and eh_frame sections
+    if (A.isInSection())
+      return !IsDebugOrEHFrameSection(A.getSection());
----------------
Should relaxation here be relocation?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D127549/new/

https://reviews.llvm.org/D127549