[PATCH] D127495: Don't use the S30 reg for the pic code .
Umesh Kalappa via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 10 06:26:56 PDT 2022
umesh.kalappa0 updated this revision to Diff 435895.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D127495/new/
https://reviews.llvm.org/D127495
Files:
llvm/lib/Target/PowerPC/PPCCallingConv.td
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/test/CodeGen/PowerPC/pr55857.ll
Index: llvm/test/CodeGen/PowerPC/pr55857.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/pr55857.ll
@@ -0,0 +1,18 @@
+; RUN: llc --relocation-model=pic \
+; RUN: -mtriple=ppc32 < %s | FileCheck %s
+
+ at g = global i32 10, align 4
+
+; Function Attrs: noinline nounwind optnone uwtable
+define i32 @main() #0 {
+; CHECK-LABEL: main:
+; CHECK-NOT: evstdd
+entry:
+ %retval = alloca i32, align 4
+ store i32 0, ptr %retval, align 4
+ %0 = load i32, ptr @g, align 4
+ ret i32 %0
+}
+
+attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="e500" "target-features"="+spe,-altivec,-bpermd,-crbits,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-quadword-atomics,-rop-protect,-vsx" }
+
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -253,8 +253,11 @@
return CSR_SVR432_VSRP_SaveList;
if (Subtarget.hasAltivec())
return CSR_SVR432_Altivec_SaveList;
- else if (Subtarget.hasSPE())
+ else if (Subtarget.hasSPE()) {
+ if (TM.isPositionIndependent() && !TM.isPPC64())
+ return CSR_SVR432_SPE_NO_S30_SaveList;
return CSR_SVR432_SPE_SaveList;
+ }
return CSR_SVR432_SaveList;
}
@@ -313,7 +316,9 @@
? CSR_SVR432_VSRP_RegMask
: (Subtarget.hasAltivec()
? CSR_SVR432_Altivec_RegMask
- : (Subtarget.hasSPE() ? CSR_SVR432_SPE_RegMask
+ : (Subtarget.hasSPE() ? (TM.isPositionIndependent()
+ ? CSR_SVR432_SPE_NO_S30_RegMask
+ : CSR_SVR432_SPE_RegMask)
: CSR_SVR432_RegMask));
}
Index: llvm/lib/Target/PowerPC/PPCCallingConv.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCCallingConv.td
+++ llvm/lib/Target/PowerPC/PPCCallingConv.td
@@ -280,10 +280,17 @@
S23, S24, S25, S26, S27, S28, S29, S30, S31
)>;
+def CSR_SPE_NO_S30 : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21,
+ S22, S23, S24, S25, S26, S27, S28, S29,
+ S31
+ )>;
+
def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>;
+def CSR_SVR432_SPE_NO_S30 : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE_NO_S30)>;
+
def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
R21, R22, R23, R24, R25, R26, R27, R28,
R29, R30, R31, F14, F15, F16, F17, F18,
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