[PATCH] D127495: Don't use the S30 reg for the pic code .

[Umesh Kalappa via Phabricator via llvm-commits]

umesh.kalappa0 created this revision.
umesh.kalappa0 added reviewers: nemanjai, chmeee.
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These changes to address the https://github.com/llvm/llvm-project/issues/55857 issue .

Solution proposed was , Since R30/S30 used as pointer (32 bits ) for GOT Table in the  ppc32 ABI ,so remove from the SPE callee save register when pic enabled .

So you don't emit the  spe load and store inst  for S30.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127495

Files:
  llvm/lib/Target/PowerPC/PPCCallingConv.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -253,8 +253,11 @@
     return CSR_SVR432_VSRP_SaveList;
   if (Subtarget.hasAltivec())
     return CSR_SVR432_Altivec_SaveList;
-  else if (Subtarget.hasSPE())
+  else if (Subtarget.hasSPE()) {
+    if (TM.isPositionIndependent() && !TM.isPPC64())
+      return CSR_SVR432_SPE_NO_S30_SaveList;
     return CSR_SVR432_SPE_SaveList;
+   }
   return CSR_SVR432_SaveList;
 }
 
@@ -313,7 +316,9 @@
                ? CSR_SVR432_VSRP_RegMask
                : (Subtarget.hasAltivec()
                       ? CSR_SVR432_Altivec_RegMask
-                      : (Subtarget.hasSPE() ? CSR_SVR432_SPE_RegMask
+                      : (Subtarget.hasSPE() ? (TM.isPositionIndependent()
+						? CSR_SVR432_SPE_NO_S30_RegMask
+						: CSR_SVR432_SPE_RegMask)
                                             : CSR_SVR432_RegMask));
 }
 
Index: llvm/lib/Target/PowerPC/PPCCallingConv.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCCallingConv.td
+++ llvm/lib/Target/PowerPC/PPCCallingConv.td
@@ -280,10 +280,17 @@
                                    S23, S24, S25, S26, S27, S28, S29, S30, S31
                               )>;
 
+def CSR_SPE_NO_S30 : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21,
+				          S22, S23, S24, S25, S26, S27, S28, S29,
+					  S31
+			      )>;
+
 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
 
 def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>;
 
+def CSR_SVR432_SPE_NO_S30 : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE_NO_S30)>;
+
 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
                                      R21, R22, R23, R24, R25, R26, R27, R28,
                                      R29, R30, R31, F14, F15, F16, F17, F18,


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