[PATCH] D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.

[Yeting Kuo via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
fakepaper56 marked an inline comment as done.
Closed by commit rGf68cad908705: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs. (authored by fakepaper56).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126794/new/

https://reviews.llvm.org/D126794

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
  llvm/test/CodeGen/RISCV/rvv/vleff-rv32-readvl.ll
  llvm/test/CodeGen/RISCV/rvv/vleff-rv64-readvl.ll
  llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv32-readvl.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv64-readvl.ll
  llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir

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