[PATCH] D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 marked an inline comment as done.
fakepaper56 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1432
+    MachineInstr &MI = *I++;
+    uint64_t TSFlags = MI.getDesc().TSFlags;
+    if (isFaultFirstLoad(MI)) {
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reames wrote:
> TSFlags appears dead, remove it before commit.
Done.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:9
 //
 // This file implements a function pass that inserts VSETVLI instructions where
 // needed.
----------------
fakepaper56 wrote:
> frasercrmck wrote:
> > Should maybe update this comment as this patch feels to me a like a new distinct step that this pass does (other than the recent pre/post passes and optimizations we've added recently and haven't listed here)
> You are right. I will add some comment there.
Done.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126794/new/

https://reviews.llvm.org/D126794