[PATCH] D127354: Implement capability to optimize add negative into subtract positive in AArch64.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15422
+    SDValue RHS = N->getOperand(1);
+    KnownBits Known;
+    unsigned Depth = 0;
----------------
No need to declare Known outside of the blocks they are used in.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15425
+    if (LHS.getOpcode() == AArch64ISD::CMHI) {
+      Known = DAG.computeKnownBits(RHS, Depth + 1);
+      if (Known.isConstant() && Known.getConstant().isOne())
----------------
Why Depth is 1 here? Shouldn't we just use the default which is 0?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127354/new/

https://reviews.llvm.org/D127354