[PATCH] D127354: Implement capability to optimize add negative into subtract positive in AArch64.

[Adrian Tong via Phabricator via llvm-commits]

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t2: v8i16 = AArch64ISD::CMHI t0, t1
t3: v8i16 = BUILD_VECTOR Constant:i32<1>, ...

  t4: v8i16 = and t2, t3
     t5: v8i16 = add t8, t4

This can be turned into t5: v8i16 = sub t8, t2, and allows us to remove
t3 and t4 from the DAG.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127354

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/add-negative.ll
  llvm/test/CodeGen/AArch64/minmax.ll

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