[PATCH] D126921: [RISCV] Untangle instruction properties from VSETVLIInfo [NFC]

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

I think the real problem is we didn't extra the abstract data from MI, so what do you think if we turn those info into more abstraction level info and still keep in `Require`?

e.g.
`MaskRegOp`: Require same ratio (VLMAX) but no matter LMUL and SEW.
`StoreOp`: No need tail/mask policy,  (Handled by `canSkipVSETVLIForLoadStore` for now) Require same ratio (VLMAX) but no matter LMUL and SEW, because EEW.
`ScalarMovOp`: Require same SEW but no matter the LMUL, and always tail-agnostic regardless VTYPE setting
`LoadOp`: (Handled by `canSkipVSETVLIForLoadStore` for now) Require same ratio (VLMAX) but no matter LMUL and SEW, because EEW.
`Any operation with mask destination`: tail elements are always treated as tail-agnostic, regardless of the setting of vta.

So the abstract info is:

- No matter LMUL?
- Require same ratio - no matter LMUL and SEW.
- Regardless tail policy of the setting of VTYPE?
- Regardless mask policy of the setting of VTYPE?

And then get rid of MI once we gather those info.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126921/new/

https://reviews.llvm.org/D126921