[llvm] 6468fea - [AArch64] Regenerate arm64-shifted-sext.ll and add a test from #55833. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 7 05:56:04 PDT 2022
Author: David Green
Date: 2022-06-07T13:55:53+01:00
New Revision: 6468feaeaca747626116e7cdf94627f7f73e7965
URL: https://github.com/llvm/llvm-project/commit/6468feaeaca747626116e7cdf94627f7f73e7965
DIFF: https://github.com/llvm/llvm-project/commit/6468feaeaca747626116e7cdf94627f7f73e7965.diff
LOG: [AArch64] Regenerate arm64-shifted-sext.ll and add a test from #55833. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll b/llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll
index cbdf6d3dd30a7..1af0384eede0c 100644
--- a/llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll
@@ -1,12 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
;
; <rdar://problem/13820218>
define signext i16 @extendedLeftShiftcharToshortBy4(i8 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedLeftShiftcharToshortBy4:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfiz w0, [[REG]], #4, #8
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfiz w0, w8, #4, #8
+; CHECK-NEXT: ret
+entry:
%inc = add i8 %a, 1
%conv1 = sext i8 %inc to i32
%shl = shl nsw i32 %conv1, 4
@@ -15,10 +18,12 @@ entry:
}
define signext i16 @extendedRightShiftcharToshortBy4(i8 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedRightShiftcharToshortBy4:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfx w0, [[REG]], #4, #4
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfx w0, w8, #4, #4
+; CHECK-NEXT: ret
+entry:
%inc = add i8 %a, 1
%conv1 = sext i8 %inc to i32
%shr4 = lshr i32 %conv1, 4
@@ -27,10 +32,12 @@ entry:
}
define signext i16 @extendedLeftShiftcharToshortBy8(i8 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedLeftShiftcharToshortBy8:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfiz w0, [[REG]], #8, #8
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfiz w0, w8, #8, #8
+; CHECK-NEXT: ret
+entry:
%inc = add i8 %a, 1
%conv1 = sext i8 %inc to i32
%shl = shl nsw i32 %conv1, 8
@@ -39,11 +46,13 @@ entry:
}
define signext i16 @extendedRightShiftcharToshortBy8(i8 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedRightShiftcharToshortBy8:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sxtb [[REG]], [[REG]]
-; CHECK: asr w0, [[REG]], #8
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sxtb w8, w8
+; CHECK-NEXT: asr w0, w8, #8
+; CHECK-NEXT: ret
+entry:
%inc = add i8 %a, 1
%conv1 = sext i8 %inc to i32
%shr4 = lshr i32 %conv1, 8
@@ -52,10 +61,12 @@ entry:
}
define i32 @extendedLeftShiftcharTointBy4(i8 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedLeftShiftcharTointBy4:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfiz w0, [[REG]], #4, #8
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfiz w0, w8, #4, #8
+; CHECK-NEXT: ret
+entry:
%inc = add i8 %a, 1
%conv = sext i8 %inc to i32
%shl = shl nsw i32 %conv, 4
@@ -63,10 +74,12 @@ entry:
}
define i32 @extendedRightShiftcharTointBy4(i8 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedRightShiftcharTointBy4:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfx w0, [[REG]], #4, #4
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfx w0, w8, #4, #4
+; CHECK-NEXT: ret
+entry:
%inc = add i8 %a, 1
%conv = sext i8 %inc to i32
%shr = ashr i32 %conv, 4
@@ -74,10 +87,12 @@ entry:
}
define i32 @extendedLeftShiftcharTointBy8(i8 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedLeftShiftcharTointBy8:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfiz w0, [[REG]], #8, #8
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfiz w0, w8, #8, #8
+; CHECK-NEXT: ret
+entry:
%inc = add i8 %a, 1
%conv = sext i8 %inc to i32
%shl = shl nsw i32 %conv, 8
@@ -85,11 +100,13 @@ entry:
}
define i32 @extendedRightShiftcharTointBy8(i8 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedRightShiftcharTointBy8:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sxtb [[REG]], [[REG]]
-; CHECK: asr w0, [[REG]], #8
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sxtb w8, w8
+; CHECK-NEXT: asr w0, w8, #8
+; CHECK-NEXT: ret
+entry:
%inc = add i8 %a, 1
%conv = sext i8 %inc to i32
%shr = ashr i32 %conv, 8
@@ -97,10 +114,12 @@ entry:
}
define i64 @extendedLeftShiftcharToint64By4(i8 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedLeftShiftcharToint64By4:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfiz x0, x[[REG]], #4, #8
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfiz x0, x8, #4, #8
+; CHECK-NEXT: ret
+entry:
%inc = add i8 %a, 1
%conv = sext i8 %inc to i64
%shl = shl nsw i64 %conv, 4
@@ -108,10 +127,12 @@ entry:
}
define i64 @extendedRightShiftcharToint64By4(i8 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedRightShiftcharToint64By4:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfx x0, x[[REG]], #4, #4
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfx x0, x8, #4, #4
+; CHECK-NEXT: ret
+entry:
%inc = add i8 %a, 1
%conv = sext i8 %inc to i64
%shr = ashr i64 %conv, 4
@@ -119,10 +140,12 @@ entry:
}
define i64 @extendedLeftShiftcharToint64By8(i8 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedLeftShiftcharToint64By8:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfiz x0, x[[REG]], #8, #8
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfiz x0, x8, #8, #8
+; CHECK-NEXT: ret
+entry:
%inc = add i8 %a, 1
%conv = sext i8 %inc to i64
%shl = shl nsw i64 %conv, 8
@@ -130,11 +153,13 @@ entry:
}
define i64 @extendedRightShiftcharToint64By8(i8 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedRightShiftcharToint64By8:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sxtb x[[REG]], w[[REG]]
-; CHECK: asr x0, x[[REG]], #8
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sxtb x8, w8
+; CHECK-NEXT: asr x0, x8, #8
+; CHECK-NEXT: ret
+entry:
%inc = add i8 %a, 1
%conv = sext i8 %inc to i64
%shr = ashr i64 %conv, 8
@@ -142,10 +167,12 @@ entry:
}
define i32 @extendedLeftShiftshortTointBy4(i16 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedLeftShiftshortTointBy4:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfiz w0, [[REG]], #4, #16
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfiz w0, w8, #4, #16
+; CHECK-NEXT: ret
+entry:
%inc = add i16 %a, 1
%conv = sext i16 %inc to i32
%shl = shl nsw i32 %conv, 4
@@ -153,10 +180,12 @@ entry:
}
define i32 @extendedRightShiftshortTointBy4(i16 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedRightShiftshortTointBy4:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfx w0, [[REG]], #4, #12
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfx w0, w8, #4, #12
+; CHECK-NEXT: ret
+entry:
%inc = add i16 %a, 1
%conv = sext i16 %inc to i32
%shr = ashr i32 %conv, 4
@@ -164,10 +193,12 @@ entry:
}
define i32 @extendedLeftShiftshortTointBy16(i16 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedLeftShiftshortTointBy16:
-; CHECK: lsl [[REG:w[0-9]+]], w0, #16
-; CHECK: add w0, [[REG]], #16, lsl #12
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: lsl w8, w0, #16
+; CHECK-NEXT: add w0, w8, #16, lsl #12 ; =65536
+; CHECK-NEXT: ret
+entry:
%inc = add i16 %a, 1
%conv2 = zext i16 %inc to i32
%shl = shl nuw i32 %conv2, 16
@@ -175,11 +206,13 @@ entry:
}
define i32 @extendedRightShiftshortTointBy16(i16 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedRightShiftshortTointBy16:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sxth [[REG]], [[REG]]
-; CHECK: asr w0, [[REG]], #16
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sxth w8, w8
+; CHECK-NEXT: asr w0, w8, #16
+; CHECK-NEXT: ret
+entry:
%inc = add i16 %a, 1
%conv = sext i16 %inc to i32
%shr = ashr i32 %conv, 16
@@ -187,10 +220,12 @@ entry:
}
define i64 @extendedLeftShiftshortToint64By4(i16 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedLeftShiftshortToint64By4:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfiz x0, x[[REG]], #4, #16
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfiz x0, x8, #4, #16
+; CHECK-NEXT: ret
+entry:
%inc = add i16 %a, 1
%conv = sext i16 %inc to i64
%shl = shl nsw i64 %conv, 4
@@ -198,10 +233,12 @@ entry:
}
define i64 @extendedRightShiftshortToint64By4(i16 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedRightShiftshortToint64By4:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfx x0, x[[REG]], #4, #12
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfx x0, x8, #4, #12
+; CHECK-NEXT: ret
+entry:
%inc = add i16 %a, 1
%conv = sext i16 %inc to i64
%shr = ashr i64 %conv, 4
@@ -209,10 +246,12 @@ entry:
}
define i64 @extendedLeftShiftshortToint64By16(i16 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedLeftShiftshortToint64By16:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfiz x0, x[[REG]], #16, #16
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfiz x0, x8, #16, #16
+; CHECK-NEXT: ret
+entry:
%inc = add i16 %a, 1
%conv = sext i16 %inc to i64
%shl = shl nsw i64 %conv, 16
@@ -220,11 +259,13 @@ entry:
}
define i64 @extendedRightShiftshortToint64By16(i16 signext %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedRightShiftshortToint64By16:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sxth x[[REG]], w[[REG]]
-; CHECK: asr x0, x[[REG]], #16
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sxth x8, w8
+; CHECK-NEXT: asr x0, x8, #16
+; CHECK-NEXT: ret
+entry:
%inc = add i16 %a, 1
%conv = sext i16 %inc to i64
%shr = ashr i64 %conv, 16
@@ -232,10 +273,12 @@ entry:
}
define i64 @extendedLeftShiftintToint64By4(i32 %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedLeftShiftintToint64By4:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfiz x0, x[[REG]], #4, #32
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfiz x0, x8, #4, #32
+; CHECK-NEXT: ret
+entry:
%inc = add nsw i32 %a, 1
%conv = sext i32 %inc to i64
%shl = shl nsw i64 %conv, 4
@@ -243,10 +286,12 @@ entry:
}
define i64 @extendedRightShiftintToint64By4(i32 %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedRightShiftintToint64By4:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfx x0, x[[REG]], #4, #28
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sbfx x0, x8, #4, #28
+; CHECK-NEXT: ret
+entry:
%inc = add nsw i32 %a, 1
%conv = sext i32 %inc to i64
%shr = ashr i64 %conv, 4
@@ -254,10 +299,12 @@ entry:
}
define i64 @extendedLeftShiftintToint64By32(i32 %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedLeftShiftintToint64By32:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: lsl x0, x[[REG]], #32
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: lsl x0, x8, #32
+; CHECK-NEXT: ret
+entry:
%inc = add nsw i32 %a, 1
%conv2 = zext i32 %inc to i64
%shl = shl nuw i64 %conv2, 32
@@ -265,13 +312,28 @@ entry:
}
define i64 @extendedRightShiftintToint64By32(i32 %a) nounwind readnone ssp {
-entry:
; CHECK-LABEL: extendedRightShiftintToint64By32:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sxtw x[[REG]], w[[REG]]
-; CHECK: asr x0, x[[REG]], #32
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: add w8, w0, #1
+; CHECK-NEXT: sxtw x8, w8
+; CHECK-NEXT: asr x0, x8, #32
+; CHECK-NEXT: ret
+entry:
%inc = add nsw i32 %a, 1
%conv = sext i32 %inc to i64
%shr = ashr i64 %conv, 32
ret i64 %shr
}
+
+define i64 @sign_extend_inreg_isdef32(i64) {
+; CHECK-LABEL: sign_extend_inreg_isdef32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sbfx x0, x0, #32, #16
+; CHECK-NEXT: ret
+ %2 = lshr i64 %0, 32
+ %3 = shl i64 %2, 16
+ %4 = trunc i64 %3 to i32
+ %5 = ashr exact i32 %4, 16
+ %6 = zext i32 %5 to i64
+ ret i64 %6
+}
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