[PATCH] D127209: [SVE][AArch64] Refine hasSVEArgsOrReturn

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau created this revision.
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As described in aapcs64 (https://github.com/ARM-software/abi-aa/blob/2022Q1/aapcs64/aapcs64.rst#scalable-vector-registers) AAVPCS is used only when registers z0-z7 take an SVE argument. This fixes the case where floats occupy the lower bits of registers z0-z7 but SVE arguments in registers greater than z7 cause a function to use AAVPCS where it should use AAPCS.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127209

Files:
  llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
  llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll

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