[PATCH] D127154: [AArch64] Remove isDef32

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:869
 
     // Don't match if free 32-bit -> 64-bit zext can be used instead.
+    auto isDef32 = [](SDValue N) {
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Maybe explicitly note this is a heuristic, so it doesn't matter if it's wrong in edge cases.


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Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:209
+static bool isFreeZExtOfGPR32(MachineInstr *MI, MachineRegisterInfo *MRI) {
+  // A COPY from and FPR will become a FMOVSWr.
+  if (MI->getOpcode() == TargetOpcode::COPY &&
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It's not clear to me we'll always end up with an FMOVSWr, given copy coalescing.

You could explicitly select an FMOVSWr here, but I guess that has other consequences for register allocation...


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Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:218
+  }
+  return MI->getOpcode() > TargetOpcode::GENERIC_OP_END;
+}
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Should we check for pseudo-instructions here?  Are there any pseudo-instructions which might produce a register with undefined high bits?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127154/new/

https://reviews.llvm.org/D127154