[PATCH] D127154: [AArch64] Remove isDef32

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: t.p.northover, efriedma, jaykang10, fhahn.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
dmgreen requested review of this revision.
Herald added a project: LLVM.

isDef32 would attempt to make a guess at which SelectionDag nodes were 32bit sources, and use the nature of 32bit AArch64 instructions implicitly zeroing the upper register half to not emit zext that were expected to already be zero. This was a bit fragile though, needing to guess at the correct opcodes that do not become 32bit defs.

This patch removed isDef32, relying on the AArch64MIPeephole optimizer to remove redundant SUBREG_TO_REG nodes. A part of SelectArithExtendedRegister was left with the same logic as a heuristic to prevent some regressions from it picking less optimal sequences, and the AArch64MIPeepholeOpt needs to be taught that COPY from a FPR will become a FMOVSWr, doing the same implicit zeroing.

Fixes #55833


https://reviews.llvm.org/D127154

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
  llvm/test/CodeGen/AArch64/arm64-popcnt.ll
  llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll
  llvm/test/CodeGen/AArch64/dp1.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D127154.434607.patch
Type: text/x-patch
Size: 6729 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220606/2937f23a/attachment.bin>