[PATCH] D127115: [RFC][DAGCombine] Make sure combined nodes are added back to the worklist in topological order.

Mon Jun 6 07:49:38 PDT 2022

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While this is probably not in a state where it is ready to merge, I decided to submit this for review as per discussion with @RKSimon .

We want to move the DAGCombiner toward processing the node in topological order. Inf act, implementing such as change in the combiner itself is not a major challenge, and I have patches which can do so for quite some time now.

However, finding a path from were we are to where we want to be proved to be fairly challenging:

- Changing the order in which the nodes are processed affects the register allocator and instruction scheduling, so we get a ton of parasitic changes in the test suite.
- The combines, backends and test cases tends to overfit the current traversal order.

To quote @RKSimon:

> You're hitting a much more severe version of the issues I encountered
> trying to improve the SimplifyDemandedBits folds, such as:
>
> - different / missing canonicalization for some ops vs the InstCombine
>
> equivalent
>
> - some weird orders of pattern matches that leave some folds almost
>
> impossible to hit
>
> - some patterns need rewriting to use value tracking instead of matching
>
> specific instructions (usually sext/zext patterns of some kind)
>
> - a lot of very custom DAG folds, usually for one target instruction
>
> pattern, in generic and target-specific combines, that seem to have been
> hacks from the very beginning (I know I'm guilty of that.....)
>
> - the introduction of new instrinics abs/min/max etc. has meant that
>
> some of the DAG folds haven't been updated to account for them
>
> - we have tests for IR that DAG shouldn't actually ever meet because the
>
> middle end should have canonicalized it away and the DAG won't generate
> those patterns.
>
> - undef/poison issues are becoming more common as the middle end
>
> handling of poison matures
>
> - early signs of bitrot in some targets - some targets get little
>
> attention, others like aarch64/amdgpu are transitioning away from DAG
> develoment to GISel (very very slowly.....)

It is obvious that there needs to be some agreed upons trategy to go through this.

This patch is only part of the change required, but is likely enough to notice the problem and come up with a plan.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127115

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
  llvm/test/CodeGen/AArch64/arm64-vmul.ll
  llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-float-compares.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
  llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
  llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
  llvm/test/CodeGen/AMDGPU/ds-alignment.ll
  llvm/test/CodeGen/AMDGPU/ds_write2.ll
  llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
  llvm/test/CodeGen/AMDGPU/r600-export-fix.ll
  llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
  llvm/test/CodeGen/AMDGPU/store-local.128.ll
  llvm/test/CodeGen/AMDGPU/store-local.96.ll
  llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
  llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
  llvm/test/CodeGen/ARM/addsubcarry-promotion.ll
  llvm/test/CodeGen/ARM/dsp-mlal.ll
  llvm/test/CodeGen/ARM/neon-copy.ll
  llvm/test/CodeGen/ARM/vdup.ll
  llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
  llvm/test/CodeGen/PowerPC/combine-fneg.ll
  llvm/test/CodeGen/PowerPC/prefer-dqform.ll
  llvm/test/CodeGen/PowerPC/select_const.ll
  llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
  llvm/test/CodeGen/PowerPC/testComparesigeui.ll
  llvm/test/CodeGen/PowerPC/testComparesigeus.ll
  llvm/test/CodeGen/PowerPC/testComparesileuc.ll
  llvm/test/CodeGen/PowerPC/testComparesileui.ll
  llvm/test/CodeGen/PowerPC/testComparesileus.ll
  llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
  llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
  llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
  llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
  llvm/test/CodeGen/PowerPC/testComparesllleui.ll
  llvm/test/CodeGen/PowerPC/testComparesllleus.ll
  llvm/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll
  llvm/test/CodeGen/PowerPC/vec_shuffle.ll
  llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
  llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll
  llvm/test/CodeGen/PowerPC/vsx.ll
  llvm/test/CodeGen/RISCV/mul.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccsu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccus.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
  llvm/test/CodeGen/SystemZ/pr36164.ll
  llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
  llvm/test/CodeGen/Thumb2/mve-vqdmulh-minmax.ll
  llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll
  llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
  llvm/test/CodeGen/X86/2012-08-07-CmpISelBug.ll
  llvm/test/CodeGen/X86/addcarry.ll
  llvm/test/CodeGen/X86/avx512-build-vector.ll
  llvm/test/CodeGen/X86/avx512-hadd-hsub.ll
  llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
  llvm/test/CodeGen/X86/avx512-mask-op.ll
  llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
  llvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
  llvm/test/CodeGen/X86/bitreverse.ll
  llvm/test/CodeGen/X86/buildvec-insertvec.ll
  llvm/test/CodeGen/X86/combine-fcopysign.ll
  llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
  llvm/test/CodeGen/X86/dagcombine-select.ll
  llvm/test/CodeGen/X86/field-extract-use-trunc.ll
  llvm/test/CodeGen/X86/haddsub-undef.ll
  llvm/test/CodeGen/X86/horizontal-sum.ll
  llvm/test/CodeGen/X86/insertelement-var-index.ll
  llvm/test/CodeGen/X86/is_fpclass-fp80.ll
  llvm/test/CodeGen/X86/isel-blendi-gettargetconstant.ll
  llvm/test/CodeGen/X86/load-partial.ll
  llvm/test/CodeGen/X86/movmsk-cmp.ll
  llvm/test/CodeGen/X86/mulvi32.ll
  llvm/test/CodeGen/X86/nontemporal-3.ll
  llvm/test/CodeGen/X86/pmulh.ll
  llvm/test/CodeGen/X86/popcnt.ll
  llvm/test/CodeGen/X86/pr42727.ll
  llvm/test/CodeGen/X86/pr53419.ll
  llvm/test/CodeGen/X86/promote-vec3.ll
  llvm/test/CodeGen/X86/psubus.ll
  llvm/test/CodeGen/X86/shift-mask.ll
  llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll
  llvm/test/CodeGen/X86/shuffle-extract-subvector.ll
  llvm/test/CodeGen/X86/slow-pmulld.ll
  llvm/test/CodeGen/X86/sse-align-12.ll
  llvm/test/CodeGen/X86/sse2.ll
  llvm/test/CodeGen/X86/sse41.ll
  llvm/test/CodeGen/X86/vec_saddo.ll
  llvm/test/CodeGen/X86/vec_smulo.ll
  llvm/test/CodeGen/X86/vec_ssubo.ll
  llvm/test/CodeGen/X86/vec_uaddo.ll
  llvm/test/CodeGen/X86/vec_umulo.ll
  llvm/test/CodeGen/X86/vec_usubo.ll
  llvm/test/CodeGen/X86/vector-bitreverse.ll
  llvm/test/CodeGen/X86/vector-fshl-256.ll
  llvm/test/CodeGen/X86/vector-fshl-512.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
  llvm/test/CodeGen/X86/vector-fshr-256.ll
  llvm/test/CodeGen/X86/vector-fshr-512.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
  llvm/test/CodeGen/X86/vector-reduce-and-cmp.ll
  llvm/test/CodeGen/X86/vector-reduce-and.ll
  llvm/test/CodeGen/X86/vector-reduce-or.ll
  llvm/test/CodeGen/X86/vector-reduce-xor.ll
  llvm/test/CodeGen/X86/vector-rotate-256.ll
  llvm/test/CodeGen/X86/vector-rotate-512.ll
  llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
  llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll
  llvm/test/CodeGen/X86/vector-zext.ll
  llvm/test/CodeGen/X86/vselect-constants.ll
  llvm/test/CodeGen/X86/xor.ll