[PATCH] D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:9
 //
 // This file implements a function pass that inserts VSETVLI instructions where
 // needed.
----------------
Should maybe update this comment as this patch feels to me a like a new distinct step that this pass does (other than the recent pre/post passes and optimizations we've added recently and haven't listed here)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126794/new/

https://reviews.llvm.org/D126794