[PATCH] D126700: [MachineScheduler] Order more stores by ascending address

[Allen zhong via Phabricator via llvm-commits]

Allen added a comment.

In D126700#3559712 <https://reviews.llvm.org/D126700#3559712>, @dmgreen wrote:

> Do you have more details on where and when you expect this to be beneficial? It may not look like it from the review, but we did a fair amount of testing and benchmarking was done on D125377 <https://reviews.llvm.org/D125377> on all kinds of CPUs (in-order vs out-of-order, little vs big, etc) to make sure that it was an improvement or benign on the cases we tried. I don't think I would be against this - so long as we had a decent reason to do so. It does constrain the scheduling graph though, so we shouldn't do so unnecessarily.

Thanks @dmgreen, base on the following test case , I'll gain benefits base on the **tsv110 target (kunpeng 920)**
BTW：I have another version, which only do some refactor(keep the logic unchanged), as we don't add new store instructions STRQ and STUR, see detail on https://reviews.llvm.org/D126700?id=433075, which is better ?

  double array[0x8000];
  
  void foo (double array[], int size) {
    for (int i=0; i<size; i++) {
       array[i] = 2.0;
    }
    return;
  }
  
  int main (){
     
    for (int i=0; i<100000; i++) {
      foo (array, sizeof (array)/sizeof (array[0]));  
    }
    return 0;
  }


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https://reviews.llvm.org/D126700