[PATCH] D126854: [RISCV] Define risc-v's own register class to model FP Register.

yanming via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Jun 5 23:51:11 PDT 2022

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ym1813382441 added a comment.

In D126854#3559588 <https://reviews.llvm.org/D126854#3559588>, @frasercrmck wrote:

> Just some nits from me

Sorry I didn't notice. I have submitted it.


Repository:
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  https://reviews.llvm.org/D126854/new/

https://reviews.llvm.org/D126854

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