[PATCH] D126854: [RISCV] Define risc-v's own register class to model FP Register.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

Just some nits from me



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Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h:213
+    case RISCVRegisterClass::FPRRC:
+      if (ST->hasStdExtF())
         return 32;
----------------
Nit but with V we have a ternary but here we have an if/else (of sorts)

Maybe they should be consistent?


================
Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h:224
+    llvm_unreachable("unknown register class");
+  }
+  unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
----------------
Blank line between functions


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Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h:239
+    return RISCVRegisterClass::GPRRC;
+  };
+  const char *getRegisterClassName(unsigned ClassID) const {
----------------
Unnecessary semicolon. Also blank line between functions


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https://reviews.llvm.org/D126854