[llvm] 2e7d4b6 - [InstCombine] Add more tests for shl+lshr transforms; NFC

[via llvm-commits]

Author: chenglin.bi
Date: 2022-06-06T10:15:48+08:00
New Revision: 2e7d4b66197b40921b52af37705d4fdd7e3a6785

URL: https://github.com/llvm/llvm-project/commit/2e7d4b66197b40921b52af37705d4fdd7e3a6785
DIFF: https://github.com/llvm/llvm-project/commit/2e7d4b66197b40921b52af37705d4fdd7e3a6785.diff

LOG: [InstCombine] Add more tests for shl+lshr transforms; NFC

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/and.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll
index 3fd81b82e347..b2f43121b805 100644
--- a/llvm/test/Transforms/InstCombine/and.ll
+++ b/llvm/test/Transforms/InstCombine/and.ll
@@ -1637,6 +1637,19 @@ define i16 @shl_lshr_pow2_const_case1(i16 %x) {
 
 define i16 @shl_lshr_pow2_const_case2(i16 %x) {
 ; CHECK-LABEL: @shl_lshr_pow2_const_case2(
+; CHECK-NEXT:    [[SHL:%.*]] = shl i16 4, [[X:%.*]]
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr i16 [[SHL]], 6
+; CHECK-NEXT:    [[R:%.*]] = or i16 [[LSHR]], -9
+; CHECK-NEXT:    ret i16 [[R]]
+;
+  %shl = shl i16 4, %x
+  %lshr = lshr i16 %shl, 6
+  %r = or i16 %lshr, 65527 ; ~8
+  ret i16 %r
+}
+
+define i16 @shl_lshr_pow2_const_case3(i16 %x) {
+; CHECK-LABEL: @shl_lshr_pow2_const_case3(
 ; CHECK-NEXT:    [[SHL:%.*]] = shl i16 16, [[X:%.*]]
 ; CHECK-NEXT:    [[LSHR:%.*]] = lshr exact i16 [[SHL]], 3
 ; CHECK-NEXT:    [[R:%.*]] = or i16 [[LSHR]], -9
@@ -1648,8 +1661,8 @@ define i16 @shl_lshr_pow2_const_case2(i16 %x) {
   ret i16 %r
 }
 
-define i13 @shl_lshr_pow2_const_case3(i16 %x) {
-; CHECK-LABEL: @shl_lshr_pow2_const_case3(
+define i13 @shl_lshr_pow2_const_case4(i16 %x) {
+; CHECK-LABEL: @shl_lshr_pow2_const_case4(
 ; CHECK-NEXT:    [[SHL:%.*]] = shl i16 16, [[X:%.*]]
 ; CHECK-NEXT:    [[LSHR:%.*]] = lshr exact i16 [[SHL]], 3
 ; CHECK-NEXT:    [[R:%.*]] = trunc i16 [[LSHR]] to i13