[llvm] a0bc67e - [Hexagon] Enable IAS in the Hexagon backend
Brad Smith via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 3 15:19:53 PDT 2022
Author: Brad Smith
Date: 2022-06-03T18:15:12-04:00
New Revision: a0bc67e555f404d0e7ddb2e78cb891d96eaf913d
URL: https://github.com/llvm/llvm-project/commit/a0bc67e555f404d0e7ddb2e78cb891d96eaf913d
DIFF: https://github.com/llvm/llvm-project/commit/a0bc67e555f404d0e7ddb2e78cb891d96eaf913d.diff
LOG: [Hexagon] Enable IAS in the Hexagon backend
Reviewed By: kparzysz
Differential Revision: https://reviews.llvm.org/D123096
Added:
Modified:
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll
llvm/test/CodeGen/Hexagon/inline-asm-i1.ll
llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll
llvm/test/CodeGen/Hexagon/v6-inlasm1.ll
llvm/test/CodeGen/Hexagon/v6-inlasm2.ll
llvm/test/CodeGen/Hexagon/v6-inlasm3.ll
llvm/test/CodeGen/Hexagon/v6vec-vprint.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
index e5e5d08937ef2..f3da675623209 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
@@ -34,5 +34,4 @@ HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) {
UsesELFSectionDirectiveForBSS = true;
ExceptionsType = ExceptionHandling::DwarfCFI;
UseLogicalShr = false;
- UseIntegratedAssembler = false;
}
diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll b/llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll
index 76d7ae6ce52ec..c7c44a3856128 100644
--- a/llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll
+++ b/llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon -no-integrated-as < %s | FileCheck %s
target triple = "hexagon"
diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll b/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll
index cc1f4ce55dad5..ee5a415b10559 100644
--- a/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll
+++ b/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll
@@ -1,6 +1,6 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: r[[REG0:[0-9]+]] = usr
-; CHECK: [[REG0]] = insert(r{{[0-9]+}}, #1, #16)
+; CHECK: [[REG0]] = insert(r{{[0-9]+}},#1,#16)
target triple = "hexagon"
diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
index 5e9d2239edd68..624ab99496d4c 100644
--- a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
+++ b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon -no-integrated-as < %s | FileCheck %s
; Check that constraints q and v are handled correctly.
; CHECK: q{{.}} = vgtw(v{{.}}.w,v{{.}}.w)
diff --git a/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll b/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll
index 33e148d3244fc..f42ecf7b7756d 100644
--- a/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll
+++ b/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll
@@ -1,9 +1,9 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: r0 = #24
-; CHECK-NEXT: r1 =
+; CHECK: r1 =
; // R2 should be assigned a value from R3+.
-; CHECK-NEXT: r2 = r{{[3-9]}}
-; CHECK-NEXT: trap0
+; CHECK: r2 = r{{[3-9]}}
+; CHECK: trap0
target datalayout = "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"
target triple = "hexagon"
diff --git a/llvm/test/CodeGen/Hexagon/v6-inlasm1.ll b/llvm/test/CodeGen/Hexagon/v6-inlasm1.ll
index 135d947bf8962..105dac8f44818 100644
--- a/llvm/test/CodeGen/Hexagon/v6-inlasm1.ll
+++ b/llvm/test/CodeGen/Hexagon/v6-inlasm1.ll
@@ -1,5 +1,5 @@
; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s
-; CHECK: vmemu(r{{[0-9]+}}) = v{{[0-9]*}};
+; CHECK: vmemu(r{{[0-9]+}}+#0) = v{{[0-9]*}}
target triple = "hexagon"
diff --git a/llvm/test/CodeGen/Hexagon/v6-inlasm2.ll b/llvm/test/CodeGen/Hexagon/v6-inlasm2.ll
index 5def2da0d7b51..1e9d5268f20b3 100644
--- a/llvm/test/CodeGen/Hexagon/v6-inlasm2.ll
+++ b/llvm/test/CodeGen/Hexagon/v6-inlasm2.ll
@@ -1,5 +1,5 @@
; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s
-; CHECK: vmemu(r{{[0-9]+}}) = v{{[0-9]*}};
+; CHECK: vmemu(r{{[0-9]}}+#0) = v{{[0-9]*}}
target triple = "hexagon"
diff --git a/llvm/test/CodeGen/Hexagon/v6-inlasm3.ll b/llvm/test/CodeGen/Hexagon/v6-inlasm3.ll
index 1f4b03c87bd16..b4b305586bb6f 100644
--- a/llvm/test/CodeGen/Hexagon/v6-inlasm3.ll
+++ b/llvm/test/CodeGen/Hexagon/v6-inlasm3.ll
@@ -1,5 +1,5 @@
; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s
-; CHECK: vmemu(r{{[0-9]+}}) = v{{[0-9]*}}
+; CHECK: vmemu(r{{[0-9]}}+#0) = v{{[0-9]*}}
target triple = "hexagon"
diff --git a/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll b/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll
index 944d0891ed453..0f232e4cb41e6 100644
--- a/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll
+++ b/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s
-; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s
+; RUN: llc -no-integrated-as -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s
+; RUN: llc -no-integrated-as -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s
; generate .long XXXX which is a vector debug print instruction.
; CHECK: .long 0x1dffe0
; CHECK: .long 0x1dffe0
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