[PATCH] D126854: [RISCV] Define risc-v's own register class to model FP Register.
Kito Cheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 2 01:05:54 PDT 2022
kito-cheng added inline comments.
================
Comment at: llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll:22
; CHECK-LMUL1: LV(REG): Found max usage: 2 item
-; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
-; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 2 registers
+; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers
+; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
----------------
Curious why there is still `GPRRC` here? I thought that should be `FPRRC` after this patch?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D126854/new/
https://reviews.llvm.org/D126854
More information about the llvm-commits
mailing list