[PATCH] D126854: [RISCV] Define risc-v's own register class to model FP Register.

[yanming via Phabricator via llvm-commits]

ym1813382441 updated this revision to Diff 433676.
ym1813382441 added a comment.

Corrected half-precision floating point.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126854/new/

https://reviews.llvm.org/D126854

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D126854.433676.patch
Type: text/x-patch
Size: 5024 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220602/1b38e6d0/attachment.bin>