[PATCH] D126565: [RegisterClassInfo] Invalidate cached information if ignoreCSRForAllocationOrder changes

[Quentin Colombet via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1a155ee7de3b: [RegisterClassInfo] Invalidate cached information if… (authored by qcolombet).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126565/new/

https://reviews.llvm.org/D126565

Files:
  llvm/include/llvm/CodeGen/RegisterClassInfo.h
  llvm/lib/CodeGen/RegisterClassInfo.cpp


Index: llvm/lib/CodeGen/RegisterClassInfo.cpp
===================================================================
--- llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -43,9 +43,11 @@
   bool Update = false;
   MF = &mf;
 
+  auto &STI = MF->getSubtarget();
+
   // Allocate new array the first time we see a new target.
-  if (MF->getSubtarget().getRegisterInfo() != TRI) {
-    TRI = MF->getSubtarget().getRegisterInfo();
+  if (STI.getRegisterInfo() != TRI) {
+    TRI = STI.getRegisterInfo();
     RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
     Update = true;
   }
@@ -67,6 +69,18 @@
   }
   CalleeSavedRegs = CSR;
 
+  // Even if CSR list is same, we could have had a different allocation order
+  // if ignoreCSRForAllocationOrder is evaluated differently.
+  BitVector CSRHintsForAllocOrder(TRI->getNumRegs());
+  for (const MCPhysReg *I = CSR; *I; ++I)
+    for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
+      CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI);
+  if (IgnoreCSRForAllocOrder.size() != CSRHintsForAllocOrder.size() ||
+      IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
+    Update = true;
+    IgnoreCSRForAllocOrder = CSRHintsForAllocOrder;
+  }
+
   RegCosts = TRI->getRegisterCosts(*MF);
 
   // Different reserved registers?
Index: llvm/include/llvm/CodeGen/RegisterClassInfo.h
===================================================================
--- llvm/include/llvm/CodeGen/RegisterClassInfo.h
+++ llvm/include/llvm/CodeGen/RegisterClassInfo.h
@@ -60,6 +60,10 @@
   // Map register alias to the callee saved Register.
   SmallVector<MCPhysReg, 4> CalleeSavedAliases;
 
+  // Indicate if a specified callee saved register be in the allocation order
+  // exactly as written in the tablegen descriptions or listed later.
+  BitVector IgnoreCSRForAllocOrder;
+
   // Reserved registers in the current MF.
   BitVector Reserved;
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D126565.433594.patch
Type: text/x-patch
Size: 1947 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220602/d19efddc/attachment.bin>