[PATCH] D126809: [ARM64EC 8/?] Implement ARM64EC "thunk" calling conventions

Wed Jun 1 16:11:10 PDT 2022

dpaoliello added inline comments.

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Comment at: llvm/lib/Target/AArch64/AArch64CallingConvention.td:247-252
+  CCIfType<[f16],
+           CCAssignToRegWithShadow<[H0, H1, H2, H3],
+                                   [X0, X1, X2, X2]>>,
+  CCIfType<[f32],
+           CCAssignToRegWithShadow<[S0, S1, S2, S3],
+                                   [X0, X1, X2, X2]>>,
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I'm not sure that this is correct: x64 doesn't have a way to read half- or single-precision floating point numbers, and (as I understand it) AArch64 half/single-precision floating point register writes don't modify the upper-bits. What happens on x64 when you write an f16/f32 to an XMM register? I assume that it gets sign-extended...

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Comment at: llvm/lib/Target/AArch64/AArch64CallingConvention.td:263
+  // convention requires "this" to be passed in RCX.
+  // FIXME: Do we need a ARM64EC_Thunk_thiscall convention?
+  // CCIfCC<"CallingConv::X86_ThisCall",
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I'll get some clarification on this...

Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126809/new/

https://reviews.llvm.org/D126809