[PATCH] D77804: [DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a subscriber: uweigand.
RKSimon added inline comments.


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Comment at: llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll:139
+; CHECK-NEXT:    st %r4, 8(%r3)
 ; CHECK-NEXT:    stg %r1, 0(%r3)
 ; CHECK-NEXT:    br %r14
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@jonpa @uweigand These tests are proving very fragile depending on the order of and/shifts - should SystemZ be preferring masking leading/trailing bits with shift-pairs over shift+and / and+shift do you think? We have TLI::shouldFoldConstantShiftPairToMask to hand that.


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  https://reviews.llvm.org/D77804/new/

https://reviews.llvm.org/D77804