[PATCH] D126487: [SVE] Fixed custom lowering of ISD::INSERT_SUBVECTOR.

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11480
 
-    EVT WideVT;
-    SDValue ExtVec;
+    EVT NarrowVT = getPackedSVEVectorVT(VT.getVectorElementCount());
+    EVT WideVT = getPackedSVEVectorVT(InVT.getVectorElementCount());
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paulwalker-arm wrote:
> david-arm wrote:
> > Are these names the wrong way around? I would have expected the wider `VT` to be called `WideVT`. We're inserting a narrower InVT subvector into a wider VT vector.
> It's wider in the context of the element type since both types have the same total bit length. `WideVT` is the wider VT because it's created based on the element count.  `InVT` (i.e. the subvector) has fewer elements than `VT` and thus its element type will need to be wider in order to match the total bit length of `NarrowVT`.
OK, fair enough. So the width or narrowness refers to the element types then? I just found it really confusing that's all, as intuitively I was expecting an insert subvector operation to insert a narrower VT into a wider one. I guess what you actually mean here is WideElementVT and NarrowElementVT. I was thinking of widening in the legalisation sense, i.e. widen a <vscale x 3 x f32> -> <vscale x 4 x f32>.


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  https://reviews.llvm.org/D126487/new/

https://reviews.llvm.org/D126487