[PATCH] D126635: [RISCV] Fix a few corner case bugs in RISCVMergeBaseOffsetOpt::matchLargeOffset

[Craig Topper via Phabricator via llvm-commits]

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The immediate for LUI is stored as 20-bit unsigned value. We need
to sign extend if after shifting by 12 to match the instruction
behavior.

If we find an LUI+ADDI on RV64, it means the constant isn't a
simm32. If it was we would have emitted LUI+ADDIW from constant
materialization. Make sure the constant is a simm32 before folding.
This appears to match gcc.

A future patch will add support for LUI+ADDIW on RV64.

Test cases have not been committd yet. Patch shows the diffs


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126635

Files:
  llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
  llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

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