[PATCH] D126588: [RISCV] isel (add (and X, 0x1FFFFFFFE), Y) as (SH1ADD (SRLI X, 1), Y)

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM as is.

And a thought for you; is there a more generic form of this?

Instead of going straight to shNadd, could we use zext.w instead?  Something along the lines of:
srli a0, a0, N // mask low
zext.w a0, a0 // mask high
slli a0, a0, N // restore position
add a0, a0, a1 // add other value

The first three seem like a generic pattern for and X, C is any contiguous 32 bit mask.

>From this form, we could then recognize the shNadd from the last three right?

Not sure if this works, and if it does, not a required follow up.  Just an idea for you to think about.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126588/new/

https://reviews.llvm.org/D126588