[PATCH] D126532: [SVE] Add a DAG combiner fold to visitADD for vscale with truncate

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2622
       (N1.getOpcode() == ISD::VSCALE)) {
+    assert(VT == MVT::i64 && "Unexpected element type!");
     const APInt &VS0 = N0.getOperand(1)->getConstantOperandAPInt(0);
----------------
You can't assert that VSCALE returns an i64.  Probably not even on Arm, but definitely not in target-independent code.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2631
+  // to a+truncate(vscale(c1+c2))
+  if (VT.isScalarInteger() && VT.getSizeInBits() < 64 &&
+      (N0.getOpcode() == ISD::ADD) &&
----------------
Do you really need to explicitly use the number "64" to make this work?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126532/new/

https://reviews.llvm.org/D126532