[PATCH] D126532: [SVE] Add a DAG combiner fold to visitADD for vscale with truncate

[Allen zhong via Phabricator via llvm-commits]

Allen created this revision.
Allen added reviewers: sdesmalen, efriedma, kmclaughlin, david-arm.
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Fold a+truncate(vscale(c1))+truncate(vscale(c2)) to a+truncate(vscale(c1+c2))
As the vscale Constant is legalized with type i64 DAG, so it inserts a truncate
in function LowerVSCALE, which cause the mismatch in D82792 <https://reviews.llvm.org/D82792>.


https://reviews.llvm.org/D126532

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/sve-vscale-combine.ll


Index: llvm/test/CodeGen/AArch64/sve-vscale-combine.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-vscale-combine.ll
+++ llvm/test/CodeGen/AArch64/sve-vscale-combine.ll
@@ -95,3 +95,17 @@
  %shl = shl i32 %vscale, 4
  ret i32 %shl
 }
+
+; Fold a+truncate(vscale(c1))+truncate(vscale(c2)) to a+truncate(vscale(c1+c2))
+define i32 @combine_add_vscale_C_i32(i32 %index) nounwind {
+; CHECK-LABEL: combine_add_vscale_C_i32:
+; CHECK-NEXT:    cntd x8, all, mul #5
+; CHECK-NEXT:    add w0, w0, w8
+; CHECK-NEXT:    ret
+  %vscale = call i32 @llvm.vscale.i32()
+  %mul8 = mul i32 %vscale, 8
+  %mul2 = mul i32 %vscale, 2
+  %index.next = add nuw i32 %index, %mul8
+  %add = add nuw i32 %index.next, %mul2
+  ret i32 %add
+}
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2619,12 +2619,29 @@
   if ((N0.getOpcode() == ISD::ADD) &&
       (N0.getOperand(1).getOpcode() == ISD::VSCALE) &&
       (N1.getOpcode() == ISD::VSCALE)) {
+    assert(VT == MVT::i64 && "Unexpected element type!");
     const APInt &VS0 = N0.getOperand(1)->getConstantOperandAPInt(0);
     const APInt &VS1 = N1->getConstantOperandAPInt(0);
     SDValue VS = DAG.getVScale(DL, VT, VS0 + VS1);
     return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), VS);
   }
 
+  // fold a+truncate(vscale(c1))+truncate(vscale(c2))
+  // to a+truncate(vscale(c1+c2))
+  if (VT.isScalarInteger() && VT.getSizeInBits() < 64 &&
+      (N0.getOpcode() == ISD::ADD) &&
+      (N0.getOperand(1).getOpcode() == ISD::TRUNCATE) &&
+      (N0.getOperand(1).getOperand(0).getOpcode() == ISD::VSCALE) &&
+      (N1.getOpcode() == ISD::TRUNCATE) &&
+      (N1.getOperand(0).getOpcode() == ISD::VSCALE)) {
+    const APInt &VS0 =
+        N0.getOperand(1).getOperand(0)->getConstantOperandAPInt(0);
+    const APInt &VS1 = N1.getOperand(0)->getConstantOperandAPInt(0);
+    SDValue VS =
+        DAG.getZExtOrTrunc(DAG.getVScale(DL, MVT::i64, VS0 + VS1), DL, VT);
+    return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), VS);
+  }
+
   // Fold (add step_vector(c1), step_vector(c2)  to step_vector(c1+c2))
   if (N0.getOpcode() == ISD::STEP_VECTOR &&
       N1.getOpcode() == ISD::STEP_VECTOR) {


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