[PATCH] D126505: [AArch64][SVE] Don't crash on pre-legalized types in extload combine.

[Ahmed Bougacha via Phabricator via llvm-commits]

ab created this revision.
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This was assuming the vector types were MVTs, but they don't have to be.

Note that the concrete output of the test isn't very useful, since it's dominated by nonsensical calling convention lowering for the weird types (ideas for a less gross test welcome!)

An alternative to consider is whether it makes sense to try this that early, but we get to this from the generic ext-load combines, so I guess it's fine on that side


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126505

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll


Index: llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll
+++ llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll
@@ -30,6 +30,15 @@
   ret <4 x i32> %val
 }
 
+; Don't try to use SVE for irregular types.
+define <2 x i256> @load_zext_v2i64i256(<2 x i64>* %ap) #0 {
+  ; CHECK-LABEL: load_zext_v2i64i256
+  ; CHECK-NOT: ptrue
+  %a = load <2 x i64>, <2 x i64>* %ap
+  %val = zext <2 x i64> %a to <2 x i256>
+  ret <2 x i256> %val
+}
+
 define <8 x i32> @load_zext_v8i16i32(<8 x i16>* %ap) #0 {
   ; CHECK-LABEL: load_zext_v8i16i32
   ; CHECK: ptrue [[P0:p[0-9]+]].s, vl8
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -5417,7 +5417,7 @@
 
 bool AArch64TargetLowering::useSVEForFixedLengthVectorVT(
     EVT VT, bool OverrideNEON) const {
-  if (!VT.isFixedLengthVector())
+  if (!VT.isFixedLengthVector() || !VT.isSimple())
     return false;
 
   // Don't use SVE for vectors we cannot scalarize if required.


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