[PATCH] D126465: [RISCV] Use knowledge of VLEN to avoid over-aligning the stack

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D126465#3540602 <https://reviews.llvm.org/D126465#3540602>, @craig.topper wrote:

> In D126465#3540599 <https://reviews.llvm.org/D126465#3540599>, @reames wrote:
>
>> I'm a bit confused by this patch.  Where does the VLEN > 32 bit come from?  All I kind find in the spec is that VLEN >= ELEN, and must be a power of 2.  Given ELEN only has to be 8, shouldn't the smallest VLEN also be 8?  This seems like an utterly useless configuration, but the spec seems to allow it?
>
> VLEN is determined by the Zvl32b, Zvl64b, Zvl128b, etc. extensions. V implies Zvl128b. Zve64* implies Zvl64b. Zve32* implies Zvl32b. VLEN can never be less than 32 with the currently defined extensions.

Thanks for the pointer.  The wording here is as follows:
"Note: Explicit use of the Zvl32b extension string is not required for any standard vector extension as they all effectively mandate at least this minimum, but the string can be useful when stating hardware capabilities."

Reviewing 18.2 and 18.3 confirms that none of the proposed vector variants allow VLEN < 32.


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