[PATCH] D77804: [DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll:185
 	%tmp7 = or i32 %tmp5, %tmp2		; <i32> [#uses=1]
 	ret i32 %tmp7
 }
----------------
same problem - instcombine will have already optimized this to:
```
define i32 @test10(i32 %p0) {
  %tmp1 = lshr i32 %p0, 7
  %tmp2 = and i32 %tmp1, 16253176
  %tmp4 = lshr i32 %p0, 12
  %tmp5 = and i32 %tmp4, 458759
  %tmp7 = or i32 %tmp5, %tmp2
  ret i32 %tmp7
}
```
It feels like I'm avoiding the issue - but should I update the arm/thumb2 UXTB16 tests to match what the middle-end will have generated?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D77804/new/

https://reviews.llvm.org/D77804