[PATCH] D77804: [DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a reviewer: dmgreen.
RKSimon added inline comments.


================
Comment at: llvm/test/CodeGen/ARM/uxtb.ll:112
+; CHECK-NEXT:    orr r0, r0, r1
 ; CHECK-NEXT:    bx lr
   %tmp1 = lshr i32 %p0, 7
----------------
RKSimon wrote:
> I'm going to take a look at this, but I'm really not familiar with the UXTB matching code, so any pointers would be appreciated.
instcombine optimises this as well:
```
define i32 @test10(i32 %p0) {
  %tmp1 = lshr i32 %p0, 7
  %tmp2 = and i32 %tmp1, 16253176
  %tmp4 = lshr i32 %p0, 12
  %tmp5 = and i32 %tmp4, 458759
  %tmp7 = or i32 %tmp5, %tmp2
  ret i32 %tmp7
}
```
which has the same problem:
```
_test10:
@ %bb.0:
        mov     r1, #248
        mov     r2, #7
        orr     r1, r1, #16252928
        orr     r2, r2, #458752
        and     r1, r1, r0, lsr #7
        and     r0, r2, r0, lsr #12
        orr     r0, r0, r1
        bx      lr
```


Repository:
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  https://reviews.llvm.org/D77804/new/

https://reviews.llvm.org/D77804