[PATCH] D126371: [SLP]Fix PR55688: Miscompile due to incorrect nuw handling.
Alexey Bataev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 25 05:30:48 PDT 2022
ABataev created this revision.
ABataev added reviewers: RKSimon, mkazantsev.
Herald added subscribers: vporpo, hiraditya.
Herald added a project: All.
ABataev requested review of this revision.
Herald added a project: LLVM.
Need gto use all ReductionOps when propagating flags for the reduction
ops, otherwise transformation is not correct.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D126371
Files:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
Index: llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
===================================================================
--- llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
+++ llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
@@ -1001,8 +1001,8 @@
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <4 x i32> [[TMP2]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = sext <4 x i1> [[TMP4]] to <4 x i32>
; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP5]])
-; CHECK-NEXT: [[OP_RDX:%.*]] = add nuw i32 [[TMP3]], [[ARG]]
-; CHECK-NEXT: [[OP_RDX2:%.*]] = add nsw i32 [[TMP6]], [[OP_RDX]]
+; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 [[TMP3]], [[ARG]]
+; CHECK-NEXT: [[OP_RDX2:%.*]] = add i32 [[TMP6]], [[OP_RDX]]
; CHECK-NEXT: ret i32 [[OP_RDX2]]
;
; THRESHOLD-LABEL: @wobble(
@@ -1016,8 +1016,8 @@
; THRESHOLD-NEXT: [[TMP4:%.*]] = icmp eq <4 x i32> [[TMP2]], zeroinitializer
; THRESHOLD-NEXT: [[TMP5:%.*]] = sext <4 x i1> [[TMP4]] to <4 x i32>
; THRESHOLD-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP5]])
-; THRESHOLD-NEXT: [[OP_RDX:%.*]] = add nuw i32 [[TMP3]], [[ARG]]
-; THRESHOLD-NEXT: [[OP_RDX2:%.*]] = add nsw i32 [[TMP6]], [[OP_RDX]]
+; THRESHOLD-NEXT: [[OP_RDX:%.*]] = add i32 [[TMP3]], [[ARG]]
+; THRESHOLD-NEXT: [[OP_RDX2:%.*]] = add i32 [[TMP6]], [[OP_RDX]]
; THRESHOLD-NEXT: ret i32 [[OP_RDX2]]
;
bb:
Index: llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
===================================================================
--- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -11031,10 +11031,6 @@
for (unsigned I = 0, E = (Sz / 2) * 2; I < E; I += 2) {
Instruction *RedOp = InstVals[I + 1].first;
Builder.SetCurrentDebugLocation(RedOp->getDebugLoc());
- ReductionOpsListType Ops;
- if (auto *Sel = dyn_cast<SelectInst>(RedOp))
- Ops.emplace_back().push_back(Sel->getCondition());
- Ops.emplace_back().push_back(RedOp);
Value *RdxVal1 = InstVals[I].second;
Value *StableRdxVal1 = RdxVal1;
auto It1 = TrackedVals.find(RdxVal1);
@@ -11046,7 +11042,7 @@
if (It2 != TrackedVals.end())
StableRdxVal2 = It2->second;
Value *ExtraRed = createOp(Builder, RdxKind, StableRdxVal1,
- StableRdxVal2, "op.rdx", Ops);
+ StableRdxVal2, "op.rdx", ReductionOps);
ExtraReds[I / 2] = std::make_pair(InstVals[I].first, ExtraRed);
}
if (Sz % 2 == 1)
@@ -11081,17 +11077,13 @@
if (ExtraReductions.size() == 1) {
Instruction *RedOp = ExtraReductions.back().first;
Builder.SetCurrentDebugLocation(RedOp->getDebugLoc());
- ReductionOpsListType Ops;
- if (auto *Sel = dyn_cast<SelectInst>(RedOp))
- Ops.emplace_back().push_back(Sel->getCondition());
- Ops.emplace_back().push_back(RedOp);
Value *RdxVal = ExtraReductions.back().second;
Value *StableRdxVal = RdxVal;
auto It = TrackedVals.find(RdxVal);
if (It != TrackedVals.end())
StableRdxVal = It->second;
VectorizedTree = createOp(Builder, RdxKind, VectorizedTree,
- StableRdxVal, "op.rdx", Ops);
+ StableRdxVal, "op.rdx", ReductionOps);
}
ReductionRoot->replaceAllUsesWith(VectorizedTree);
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