[PATCH] D126353: [X86] Add isSimple check to the load combine in combineExtractVectorElt.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 25 00:24:31 PDT 2022
craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, pengfei.
Herald added subscribers: StephenFan, hiraditya.
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craig.topper requested review of this revision.
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I think we need to be sure the load isn't volatile before we
duplicate and shrink it.
Noticed while looking at this code for other reasons. So I don't have
a test case. If we agree this is a bug I can try to add one.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D126353
Files:
llvm/lib/Target/X86/X86ISelLowering.cpp
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -43520,7 +43520,7 @@
auto *LoadVec = dyn_cast<LoadSDNode>(InputVector);
if (LoadVec && CIdx && ISD::isNormalLoad(LoadVec) && VT.isInteger() &&
SrcVT.getVectorElementType() == VT && DCI.isAfterLegalizeDAG() &&
- !LikelyUsedAsVector) {
+ !LikelyUsedAsVector && LoadVec->isSimple()) {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
SDValue NewPtr =
TLI.getVectorElementPointer(DAG, LoadVec->getBasePtr(), SrcVT, EltIdx);
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