[PATCH] D125364: [RISCV] Replace ISD::FP_EXTEND and ISD::FP_ROUND with RVV VL op.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:827
+              (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
+                 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>;
+    def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
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craig.topper wrote:
> This is taking the VL from the fpextend_vl node, but the root node of the pattern has no VL operand. Shouldn't we still be using vti.AVL?
That would cause error `dead named input: $vl`.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:1524
 // 14.3. Vector Widening Floating-Point Add/Subtract Instructions
+defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF<fadd, "PseudoVFWADD">;
+defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF<fsub, "PseudoVFWSUB">;
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craig.topper wrote:
> Don't move things to this file that use none _vl ISD opcodes. This file should be pure VL patterns.
Done, I move those patterns back to RISCVInstrInfoVSDPatterns.td.


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  https://reviews.llvm.org/D125364/new/

https://reviews.llvm.org/D125364