[llvm] 948d931 - [RISCV] Ensure the forwarded AVL register is alive

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-05-24T15:07:42-07:00
New Revision: 948d931323a13dfc68430814a44b9075a59e2310

URL: https://github.com/llvm/llvm-project/commit/948d931323a13dfc68430814a44b9075a59e2310
DIFF: https://github.com/llvm/llvm-project/commit/948d931323a13dfc68430814a44b9075a59e2310.diff

LOG: [RISCV] Ensure the forwarded AVL register is alive

When the AVL value does not fit in 5 bits, the register in which this value is stored may be dead when we want to forward it. This patch ensure the kill flags on the register are cleared before forwarding.

Patch by: loralb
Differential Revision: https://reviews.llvm.org/D125971

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 330fc8e1bca0a..2a1cdeca4af09 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1239,8 +1239,10 @@ void RISCVInsertVSETVLI::doLocalPrepass(MachineBasicBlock &MBB) {
                 MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI));
                 if (CurInfo.hasAVLImm())
                   VLOp.ChangeToImmediate(CurInfo.getAVLImm());
-                else
+                else {
+                  MRI->clearKillFlags(CurInfo.getAVLReg());
                   VLOp.ChangeToRegister(CurInfo.getAVLReg(), /*IsDef*/ false);
+                }
                 CurInfo = computeInfoForInstr(MI, TSFlags, MRI);
                 continue;
               }

diff  --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
index 4e0364e41eb74..e625e446eea04 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -521,6 +521,20 @@ declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64(
 declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64.i64(
   <vscale x 1 x i64>, i64, i64)
 
+; Ensure AVL register is alive when forwarding an AVL immediate that does not fit in 5 bits
+define <vscale x 2 x i32> @avl_forward5(<vscale x 2 x i32>* %addr) {
+; CHECK-LABEL: avl_forward5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 32
+; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu
+; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    ret
+  %gvl = tail call i64 @llvm.riscv.vsetvli.i64(i64 32, i64 0, i64 2)
+  %ret = tail call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* %addr, i64 %gvl)
+  ret <vscale x 2 x i32> %ret
+}
+
 declare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>,