[llvm] d2ee2c9 - [RISCV] Add an operand kind to the opcode/imm returned from RISCVMatInt.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue May 24 15:00:35 PDT 2022
Author: Craig Topper
Date: 2022-05-24T14:56:29-07:00
New Revision: d2ee2c9c8d34bc915a3d7c00951831eb24708f6a
URL: https://github.com/llvm/llvm-project/commit/d2ee2c9c8d34bc915a3d7c00951831eb24708f6a
DIFF: https://github.com/llvm/llvm-project/commit/d2ee2c9c8d34bc915a3d7c00951831eb24708f6a.diff
LOG: [RISCV] Add an operand kind to the opcode/imm returned from RISCVMatInt.
Instead of matching opcodes to know the format to emit, use an
enum value that we can get from the RISCVMatInt::Inst class.
Change the consumers to use fully covered switches so that we get
a compiler warning if a new kind is added. With the opcode checks
it was easier to forget to update one of the 3 consumers.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D126317
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index ffa30b27756f9..08f0d062d215a 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2318,23 +2318,26 @@ void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
MCRegister SrcReg = RISCV::X0;
for (RISCVMatInt::Inst &Inst : Seq) {
- if (Inst.Opc == RISCV::LUI) {
+ switch (Inst.getOpndKind()) {
+ case RISCVMatInt::Imm:
+ emitToStreamer(Out,
+ MCInstBuilder(Inst.Opc).addReg(DestReg).addImm(Inst.Imm));
+ break;
+ case RISCVMatInt::RegX0:
emitToStreamer(
- Out, MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Inst.Imm));
- } else if (Inst.Opc == RISCV::ADD_UW) {
- emitToStreamer(Out, MCInstBuilder(RISCV::ADD_UW)
- .addReg(DestReg)
- .addReg(SrcReg)
- .addReg(RISCV::X0));
- } else if (Inst.Opc == RISCV::SH1ADD || Inst.Opc == RISCV::SH2ADD ||
- Inst.Opc == RISCV::SH3ADD) {
+ Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addReg(
+ RISCV::X0));
+ break;
+ case RISCVMatInt::RegReg:
emitToStreamer(
Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addReg(
SrcReg));
- } else {
+ break;
+ case RISCVMatInt::RegImm:
emitToStreamer(
Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm(
Inst.Imm));
+ break;
}
// Only the first instruction has X0 as its source.
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index ea74dde6f715a..d19da6bd36646 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -394,5 +394,30 @@ int getIntMatCost(const APInt &Val, unsigned Size,
}
return std::max(1, Cost);
}
+
+OpndKind Inst::getOpndKind() const {
+ switch (Opc) {
+ default:
+ llvm_unreachable("Unexpected opcode!");
+ case RISCV::LUI:
+ return RISCVMatInt::Imm;
+ case RISCV::ADD_UW:
+ return RISCVMatInt::RegX0;
+ case RISCV::SH1ADD:
+ case RISCV::SH2ADD:
+ case RISCV::SH3ADD:
+ return RISCVMatInt::RegReg;
+ case RISCV::ADDI:
+ case RISCV::ADDIW:
+ case RISCV::SLLI:
+ case RISCV::SRLI:
+ case RISCV::SLLI_UW:
+ case RISCV::RORI:
+ case RISCV::BSETI:
+ case RISCV::BCLRI:
+ return RISCVMatInt::RegImm;
+ }
+}
+
} // namespace RISCVMatInt
} // namespace llvm
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
index 6a8e0c6400012..90c29f01c43d8 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
@@ -17,11 +17,21 @@ namespace llvm {
class APInt;
namespace RISCVMatInt {
+
+enum OpndKind {
+ RegImm, // ADDI/ADDIW/SLLI/SRLI/BSETI/BCLRI
+ Imm, // LUI
+ RegReg, // SH1ADD/SH2ADD/SH3ADD
+ RegX0, // ADD_UW
+};
+
struct Inst {
unsigned Opc;
int64_t Imm;
Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {}
+
+ OpndKind getOpndKind() const;
};
using InstSeq = SmallVector<Inst, 8>;
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index b45de2ff6f818..7d6e27f8e7808 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -188,16 +188,21 @@ static SDNode *selectImm(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT,
SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT);
for (RISCVMatInt::Inst &Inst : Seq) {
SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, XLenVT);
- if (Inst.Opc == RISCV::LUI)
- Result = CurDAG->getMachineNode(RISCV::LUI, DL, XLenVT, SDImm);
- else if (Inst.Opc == RISCV::ADD_UW)
- Result = CurDAG->getMachineNode(RISCV::ADD_UW, DL, XLenVT, SrcReg,
+ switch (Inst.getOpndKind()) {
+ case RISCVMatInt::Imm:
+ Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SDImm);
+ break;
+ case RISCVMatInt::RegX0:
+ Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg,
CurDAG->getRegister(RISCV::X0, XLenVT));
- else if (Inst.Opc == RISCV::SH1ADD || Inst.Opc == RISCV::SH2ADD ||
- Inst.Opc == RISCV::SH3ADD)
+ break;
+ case RISCVMatInt::RegReg:
Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SrcReg);
- else
+ break;
+ case RISCVMatInt::RegImm:
Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SDImm);
+ break;
+ }
// Only the first instruction has X0 as its source.
SrcReg = SDValue(Result, 0);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index b3e6cd8a915a7..3e5948f8ff169 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -651,27 +651,32 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
assert(!Seq.empty());
for (RISCVMatInt::Inst &Inst : Seq) {
- if (Inst.Opc == RISCV::LUI) {
- BuildMI(MBB, MBBI, DL, get(RISCV::LUI), DstReg)
+ switch (Inst.getOpndKind()) {
+ case RISCVMatInt::Imm:
+ BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
.addImm(Inst.Imm)
.setMIFlag(Flag);
- } else if (Inst.Opc == RISCV::ADD_UW) {
- BuildMI(MBB, MBBI, DL, get(RISCV::ADD_UW), DstReg)
+ break;
+ case RISCVMatInt::RegX0:
+ BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
.addReg(SrcReg, RegState::Kill)
.addReg(RISCV::X0)
.setMIFlag(Flag);
- } else if (Inst.Opc == RISCV::SH1ADD || Inst.Opc == RISCV::SH2ADD ||
- Inst.Opc == RISCV::SH3ADD) {
+ break;
+ case RISCVMatInt::RegReg:
BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
.addReg(SrcReg, RegState::Kill)
.addReg(SrcReg, RegState::Kill)
.setMIFlag(Flag);
- } else {
+ break;
+ case RISCVMatInt::RegImm:
BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
.addReg(SrcReg, RegState::Kill)
.addImm(Inst.Imm)
.setMIFlag(Flag);
+ break;
}
+
// Only the first instruction has X0 as its source.
SrcReg = DstReg;
}
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