[PATCH] D126112: [BOLT] Increase coverage of shrink wrapping [2/5]

[Rafael Auler via Phabricator via llvm-commits]

rafauler created this revision.
rafauler added reviewers: Amir, maksfb, yota9, ayermolo, zr33.
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Increase coverage of isStackAccess(), making frame opt able
to analyze more functions.

While this has been empirically determined to be one of the most
frequent instructions that need to be analyzed by shrink wrapping in
our use cases, it would be great to have a way of deriving this
information automatically, based on TableGen. I'm not sure this can be
done at the moment, so we rely expanding our logic here.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126112

Files:
  bolt/lib/Target/X86/X86MCPlusBuilder.cpp


Index: bolt/lib/Target/X86/X86MCPlusBuilder.cpp
===================================================================
--- bolt/lib/Target/X86/X86MCPlusBuilder.cpp
+++ bolt/lib/Target/X86/X86MCPlusBuilder.cpp
@@ -1073,14 +1073,59 @@
       I = {Sz, IsLoad, IsStore, false, false};
       break;
     }
+    // TODO: Find a way to encode this info into tablegen somehow / fetch via MC
+    // We need to query how wide, in bytes, is the memory access of a given inst
+    case X86::MOV8rm: I = {1, true, false, false, true}; break;
     case X86::MOV16rm: I = {2, true, false, false, true}; break;
     case X86::MOV32rm: I = {4, true, false, false, true}; break;
     case X86::MOV64rm: I = {8, true, false, false, true}; break;
+    case X86::MOVZX32rm8: I = {1, true, false, false, false}; break;
+    case X86::MOVZX32rm16: I = {2, true, false, false, false}; break;
+    case X86::FNSTCW16m: I = {2, true, false, false, false}; break;
+    case X86::ILD_F32m: I = {4, true, false, false, false}; break;
+    case X86::ILD_F64m: I = {8, true, false, false, false}; break;
+    case X86::LD_F32m: I = {4, true, false, false, false}; break;
+    case X86::LD_F64m: I = {8, true, false, false, false}; break;
+    case X86::LD_F80m: I = {10, true, false, false, false}; break;
+    case X86::MOV8mr: I = {1, false, true, true, true};  break;
     case X86::MOV16mr: I = {2, false, true, true, true};  break;
     case X86::MOV32mr: I = {4, false, true, true, true};  break;
     case X86::MOV64mr: I = {8, false, true, true, true};  break;
+    case X86::ST_FP32m: I = {4, false, true, false, false};  break;
+    case X86::ST_FP64m: I = {8, false, true, false, false};  break;
+    case X86::ST_FP80m: I = {10, false, true, false, false};  break;
+    case X86::SETCCm: I = {1, false, true, false, false}; break;
+    case X86::MOV8mi: I = {1, false, true, false, true}; break;
     case X86::MOV16mi: I = {2, false, true, false, true}; break;
     case X86::MOV32mi: I = {4, false, true, false, true}; break;
+    case X86::INC32m: I = {4, true, true, false, false}; break;
+    case X86::INC64m: I = {8, true, true, false, false}; break;
+    case X86::DEC32m: I = {4, true, true, false, false}; break;
+    case X86::DEC64m: I = {8, true, true, false, false}; break;
+    case X86::OR8mi: I = {1, true, true, false, false}; break;
+    case X86::OR16mi: I = {2, true, true, false, false}; break;
+    case X86::OR32mi: I = {4, true, true, false, false}; break;
+    case X86::AND8mi: I = {1, true, true, false, false}; break;
+    case X86::AND16mi: I = {2, true, true, false, false}; break;
+    case X86::AND32mi: I = {4, true, true, false, false}; break;
+    case X86::DIV64m: I = {8, true, false, false, false}; break;
+    case X86::IMUL64m: I = {8, true, false, false, false}; break;
+    case X86::SUB32mi8: I = {4, true, true, false, false}; break;
+    case X86::SUB64mi8: I = {8, true, true, false, false}; break;
+    case X86::SUB64mi32: I = {8, true, true, false, false}; break;
+    case X86::SHL64mi: I = {8, true, true, false, false}; break;
+    case X86::SAR64mi: I = {8, true, true, false, false}; break;
+    case X86::ADD32mi8: I = {4, true, true, false, false}; break;
+    case X86::ADD64mi8: I = {8, true, true, false, false}; break;
+    case X86::ADD64mi32: I = {8, true, true, false, false}; break;
+    case X86::CMP16mi8: I = {2, true, false, false, false}; break;
+    case X86::CMP32mi8: I = {4, true, false, false, false}; break;
+    case X86::CMP32mi: I = {4, true, false, false, false}; break;
+    case X86::CMP64mi8: I = {8, true, false, false, false}; break;
+    case X86::TEST8mi: I = {1, true, false, false, false}; break;
+    case X86::TEST64mi32: I = {8, true, false, false, false}; break;
+    case X86::CMP8mi: I = {1, true, false, false, false}; break;
+    case X86::MOV64mi32: I = {8, true, false, false, false}; break;
     } // end switch (Inst.getOpcode())
 
     unsigned BaseRegNum;


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